Question

Use this bit of code for questions 1 and 2.

            add $5, $7, $2

            sw $9, 4($6)

            lw $4, 8($12)                                              

            or $6, $5, $3

Assume that the code is stored starting at 0x00600000, the values in the memory are all initially -1, and the register values are the same as the number (so $5 holds the value 5). Using the pipelined diagram, give the contents of each internal register at the end of the 4th clock cycle. Be specific and give the actual values placed into the register. The gray area indicates that there is no value at that point.

Read data 1
Read data 2
Sign Extend
ALU Result
Read data

For the code, complete the control as it would be stored into the ID/EX, EX/MEM and MEM/WB registers at the end of clock cycle 4. If the control is not in that register, leave the control blank.

Instr	RegDest	ALUSrc	Mem to Reg	Reg Write	Mem Read	Mem Write	Branch	ALU Op1	ALU Op0
ID/EX
EX/MEM
MEM/WB

Answer 1

Answer:

Explanation of the registers and the pipelined registers: Program Counter (PC): It holds the address of the instruction which is to be executed next. In instruction fetch stage, the instruction is read from the memory using the address in the PC and placed it in the IF/ID pipeline register. Read data 1, read data 2 and sign-extend: The instruction fetched in the IF/ID stage provides register numbers to read two registers and extends the sign of the 16-bit immediate number. Now, the 32-bit values of two registers (read data 1, read data 2) and immediate are placed in an ID/EX pipelined register. Zero: The zero output from the ALU represents the equality of the two inputs. If the two inputs of the ALU are identical, the Zero output of the ALU is 1. ALU result: It is one of the outputs of the ALU. It is controlled by the ALU control signal and performs arithmetic and logic instructions. Read data: It is used when the instruction used is a load. The load instruction needs to read the data from the memory to a required register. Consider the given code as shown below: add $5, $7, $2 sw $9, 4($6) lw $4, 8($12) or $6, $5, $3 The contents of the internal registers at the end of the 4th clock cycle of the pipeline is given below:

| Clock cycle 1 IF/ID Ox0060 0004 Clock cycle 2 ID/EX Ox0060 0008 Clock cycle 3 EX/MEM Ox0060 000C Clock cycle 4 MEM/WB 2 Register | PC Read data 1 Read data 2 Sign Extend Zero ALU Result Read data Ox0060 0000 At clock cycle 1, The starting address of the code is 0x00600000 and it is incremented by 4 for every clock cycle. Therefore, the PC stores the next instruction at the address 0x00600004. The instruction at the address 0x00600004 is add $5, $7, $2 and it is placed in IF/ID pipeline register. At clock cycle 2, the instruction is decoded. Then the register numbers are identified which are $2, $7. The register values are supplied to ID/EX pipeline register. Therefore, the value of read data 1 is 2, and read data 2 is 7. The 16-bit sign is extended to 32-bits. Therefore, the 0060 is extended to 0060 0000. At clock cycle 3, The operation of the instruction is performed by the ALU. The instruction adds the values 2 and 7, place the ALU result 9 in EX/MEM pipeline register. The zero output of the ALU is 0 because, the ALU output is non-zero. The first instruction is executed completely. Consider the next instruction sw $9, 4($6). At clock cycle 1, The PC is incremented by 4 and its address is 0x0060 0008. At clock cycle 3, the sw instruction reads the register value $6 as shown in read data 2. The value 6 is added to the offset 4. The resultant value is the location used to store the register value $9. At clock cycle 4, the value 9 is stored in the location 0x0060 0012. The second instruction is executed completely. The instruction lw $4, 8 ($12) is started at the address 0x0060 000C. Load the value from the location (Base address 8+12) to the register $4.

Consider the pipeline diagram for the execution of given instructions: Instruction Clock cyclel Clock cycle 2 Clock cycle 3 Clock cycle 4 Clock cycle 5 Clock cycle 6 Clock cycle 7 IF ID EX ID MEM EX add $5, $7, $2 sw $9, 4($6) lw $4, 8($12) or $6, $5, $3 WB MEM EX ID IF ID WB MEM EX IF WB MEM At clock cycle 4, the instruction add $5, $7, $2 completes the execution stage and remaining are not executed completely. Therefore, the result of add instruction is stored into the pipeline registers. Consider the given instructions and fill the table as shown below: Branch ALU Reg Mem Mem Write Read Write ALU Opl Op2 Instr RegDest ALUSrc Mem to Reg ID/EX $9 EX/MEM MEM/WB $5 $7+$2 $6 S7 T $2 $5