Question

BJT Amplifier Design Final Project Requirements: The Final Project consists of designing a cascaded BJT Amplifier, using 2 stages. The first stage will be the Common Emitter (CE) Amplifier, the second stage is the Common Collector (CC) Amplifier, as shown in the general diagram below: CE → cc The design requirements are described here: The overall amplification (voltage gain) Axotal as given to each student (each student has different total voltage gain Atotal value] The input source voltage source is an ideal source(Rs=0 Ohm) with peak voltage 10 mV, and the source frequency source=2K Hz The load resistance R = 47k Ohms Each student will have different values needed for the design (see page-2): Student Name Student ID Overall voltage gain (with load) Atotal 95 You need to make the design with proper calculations and assumptions for some of the missing values. Make sure the load line and the Q-point, Ic(sat) all designed properly. There will be theoretical & practical design as shown in the Final Project Report Template & Rubric. The theoretical design will include the calculations and the assumptions in the design. While the practical design will be building the amplifier circuit using multisim software and showing the results. More description of the BJT Amplifier design is provided in the Final Project Report Template & Rubric.

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Given Requirements: Av = 95 2K HZ input frequency RL peak Voltage 47K.22 = 10mV. Circuit Diagram: Vcc=15U Vcc = 150 RC M C G2 2N2222 A C3 2N22224 VO RB + REZ R247K Vin www ih REI CE I VEE =-15V ß ~ 200 for 2N22224 Transistors Vcc = 15V, - VEE - VEE. =-15V.

CE. First, I design:cc. Cc then Let TER IMA VEE VBE Itz Rez + RB ß+! IEZ 15 V -0.7V REZ + RB Bri 14.3K1 RE - 14,3V + RB Bri IMA Let RB = 100KR RB 1ooks 50012 11 ß+1 201 5002 REZ = 14.3k_2 REZI 13.8k se Voltage gain for cc stage is AU2 = gmz (Real Re) (+9m2 (Rezila

ama Ic2 =&ma 4omalu Vy 25mu Rezller 13,8K21) 47K-12 RE: URL 10.67K12 Avz = 40m (10.67K-12) 1 + (40m x 10.67K) Ave 0, 0916 V/v Av AVI y Ava Avi - Av - 95 AU2 0.9976 Avi 95.23 vlu = Now We design fo CE stage. Let IEI =IMA Let Ri = R2 = 100k 22 Rth Rth = R lR2 = look se ll look. Rin --50K2

Rih - 50K2. 250,82 2+) 2.00+1 Yn - ISV x 100k E V cc XR2 R,+ R2 look + look Vih 7.5v IEI Vith - UBEI RE, T Rih ß+1 IMA 7.5V - 0.7V REI + 250.12 REI +2502 !! 6.8kr REI 6.55 K2 laval = gm, (Rc ll Ro) gm, Ici = IMA asmu = 40m malu Vi 95.23 - yom (RC ll 100k ) ( Relliook ) 2.38 KD

Rc x 100K 2,38 Kn Rc t look (238x10) look Rc 2.38K Rc 1106 97.62K Rc 238 X10 Rc = 238 x106 97.62k Rc 2.438 K 22. Let the Lower cut-off frequency f =100 HZ U J ZT f Rakci Calcci = Roth 50 K_22 1 c 21T x 100 x 50K ci = 31.83 n F 1 ار) 2T f Raicę

Ral C - Rc + RB 2.438 K_1 +100KR Rac Cz 102.438k_n cu 2 TT X100 x 102,438 K 15.53 nF ca C3 2TfL (Rake (3) - (RE+ R2) 2T X 100 11 M ZITX 100x60.8K C3 26.170F CE 2Tf Raic Ce Ralc CE 11 REI Rth tres B+1 rei = U = 25mu It, =25$ IMA

Ralc Ce ſ i 6.55k (250+25) Ralc 2642 CE CE = 27 X 100 X 264 CE = 6 MF