Question

Module 10 Assignment - Direct-mapped Cache Direct-Mapped Cache In this question you're given a 16-byte memory segment and an 8-byte cache. Given the following series of memory accesses, complete the table below. Use the first Contents/Tag column to insert an item to the cache the first time and use the second Contents/Tag column if a cache entry is overwritten. Note: no index will have more than two blocks mapped to it. The first two examples have been provided. How many cache hits occurs given the memory accesses? How many cache misses are there? Additionally, what is the name of the cache eviction policy being used here? Namely, our strategy is to overwrite existing elements in the cache if cache slot is already full. In 1-2 paragraphs, discuss the performance implications (advantages/disadvantages) of using this eviction heuristic. Memory access: 0x48, 0x40, 0x46, 0x40, 0x42, 0x4B, 0x45, 0x41, 0x48, 0x4F, Ox4A, 0x47, 0x40, 0x43, Ox4C, 0x4E, Ox40, 0x49, 0x47 Memory Address Block Contents 3 a 9 R ! 8 p d Ox40 Ox41 0x42 Ox43 Ox44 0x45 Ox46 Ox47 0x48 Ox49 OX4A Ox 4B 0x40 Ox4D Ox4E Ox4F 7 ? V S A T 4 Contents Tag Contents J Tag 1001 Index 000 001 010 011 100 101 S 1001 110 111

Answer 1

Cache Type => Direct Mapped Cache

Memory Size = 16 Bytes

Cache Size = 8 Bytes

Block Size = 1 Byte

=> Byte Offset = $\small log_2(#block\;size) = log_2(1)$ = 0 bits

So, Number of cache blocks = Cache Size / Block Size = 8/1 = 8

=> Index Bits Size = $\small log_2(#cache\;blocks) = log_2(8)$ = 3 bits

Cache Index = Memory Block Number % #Cache Blocks = Memory Block Number % 8

Let's understand first memory access 0x48 and how can it map to cache block

Memory Access = 0x48

• Memory address in Binary = 0100 1000
• Cache Index = 000 => 0th Cache Block
• Tag = 01001
• Cache Miss
• Contents from memory = J

Memory Access = 0x4C

• Memory address in Binary = 0100 1100
• Cache Index = 100 => 4th Cache Block
• Tag = 01001
• Cache Miss
• Contents from memory = s

Memory Access = 0x46

• Memory address in Binary = 0100 0110
• Cache Index = 110 => 6th Cache Block
• Tag = 01000
• Cache Miss
• Contents from memory = p

Memory Access = 0x4D

• Memory address in Binary = 0100 1101
• Cache Index = 101 => 5th Cache Block
• Tag = 01001
• Cache Miss
• Contents from memory = A

Memory Access = 0x42

• Memory address in Binary = 0100 0010
• Cache Index = 010 => 2nd Cache Block
• Tag = 01000
• Cache Miss
• Contents from memory = 9

Memory Access = 0x4B

• Memory address in Binary = 0100 1011
• Cache Index = 011 => 3rd Cache Block
• Tag = 01001
• Cache Miss
• Contents from memory = V

Memory Access = 0x45

• Memory address in Binary = 0100 0101
• Cache Index = 101 => 5th Cache Block
• Tag = 01000
• Cache Miss
• Contents from memory = 8

Memory Access = 0x41

• Memory address in Binary = 0100 0001
• Cache Index = 001 => 1st Cache Block
• Tag = 01000
• Cache Miss
• Contents from memory = a

Memory Access = 0x48

• Memory address in Binary = 0100 1000
• Cache Index = 000 => 0th Cache Block
• Tag = 01001
• Cache Hit

Memory Access = 0x4F

• Memory address in Binary = 0100 1111
• Cache Index = 111 => 7th Cache Block
• Tag = 01001
• Cache Miss
• Contents from memory = 4

Memory Access = 0x4A

• Memory address in Binary = 0100 1010
• Cache Index = 010 => 2nd Cache Block
• Tag = 01001
• Cache Miss
• Contents from memory = ?

Memory Access = 0x47

• Memory address in Binary = 0100 0111
• Cache Index = 111 => 7th Cache Block
• Tag = 01000
• Cache Miss
• Contents from memory = d

Memory Access = 0x40

• Memory address in Binary = 0100 0000
• Cache Index = 000 => 0th Cache Block
• Tag = 01000
• Cache Miss
• Contents from memory = 3

Memory Access = 0x43

• Memory address in Binary = 0100 0011
• Cache Index = 011 => 3rd Cache Block
• Tag = 01000
• Cache Miss
• Contents from memory = R

Memory Access = 0x4C

• Memory address in Binary = 0100 1100
• Cache Index = 100 => 4th Cache Block
• Tag = 01001
• Cache Hit

Memory Access = 0x4E

• Memory address in Binary = 0100 1110
• Cache Index = 110 => 6th Cache Block
• Tag = 01001
• Cache Miss
• Contents from memory = T

Memory Access = 0x40

• Memory address in Binary = 0100 0000
• Cache Index = 000 => 0th Cache Block
• Tag = 01000
• Cache Hit

Memory Access = 0x49

• Memory address in Binary = 0100 1001
• Cache Index = 001 => 1st Cache Block
• Tag = 01001
• Cache Miss
• Contents from memory = 7

Memory Access = 0x47

• Memory address in Binary = 0100 0111
• Cache Index = 111 => 7th Cache Block
• Tag = 01000
• Cache Hit

Index	Contents	Tag	Contents	Tag
000	J	1001	3	1000
001	a	1000	7	1001
010	9	1000	?	1001
011	V	1001	R	1000
100	s	1001
101	A	1001	8	1000
110	p	1000	T	1001
111	4	1001	d	1000

Total Cache Misses = 15

Total Cache Hits = 4

In Direct Mapped cache, replacement policy is in-built policy as indexed slot is always replaced if it is full. There is no other choice.

The major dis-advatage of this replacement approach is that if multiple block which are mapped to same slot are continuously referenced then they will be swapped in and out multiple times which can lead to thrashing. Also the blocks which are not used for long time but mapped to different cache slot will always be present and never chosen for replacement.