1. It’s possible to get: TLB hit/ Cache miss. ------- True (T)
2. It’s possible to get: TLB miss/ Page Table hit/ Cache hit. ------ True (T)
3. It’s possible to get: TLB miss/ Page Table hit/ Cache miss. ------ True (T)
4. It’s possible to get: TLB miss/ Page Fault/ Cache hit. ------ False (F)
Explanation:
1. It’s possible to get: TLB hit/ Cache miss. ------- True (T)
Reason: If page is present in TLB, means if TLB is hit then nothing is checked. (page table should be hit in this case, if page table misses then this combination is also impossible)
2. It’s possible to get: TLB miss/ Page Table hit/ Cache hit. ------ True (T)
Reason: If TLB misses, page can be found in page table.
3. It’s possible to get: TLB miss/ Page Table hit/ Cache miss. ------ True (T)
Reason: if page is not present in TLB, page can be found in page table but it is not necessary that data should be available in cache.
4. It’s possible to get: TLB miss/ Page Fault/ Cache hit. ------ False (F)
Reason: Page fault means page is not present main memory, if page is not in memory, then how can it be inside a cache, Impossible.
Computer architecture Question 25 Answer the following about the memory system with virtual memory. Select True/False...
Question 31 supus Given a computer using a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associative cache, and a page table for a process P. Assume cache blocks of size 16 bytes. Assume pages of size 32 bytes and a main memory of 4 frames. Assume the following TLB and page table for Process P: TLB 03 4 هما 0 1 2 3 4 5 6 7 Page Table f Vali d 1 1 0 2...
7 pts Question 30 Consider a computer system that uses virtual memory with paging with a TLB. Suppose main memory access time is 10 ns and the time to look up the TLB 1 ns. Assume no page faults and the TLB has a hit of 95%. What is the effective memory access time (express in ns) 11ns
Computer Organization and Design, Risc-V Mips
Question 9 8 pts Complete the following trace of accesses to virtual addresses. In the case of page faults, continue allocating physical pages in the order Ox10000, 0x10001, Ox10002, etc. Page Physical Virtual Virtual TLB TLB PT Physical address page num hit/miss entry index fault page num address Ох00002040| Ох00002 Ox00011040 hit 2 Ox00011 OX000067CC Ox00006 Ox00080 0X000807CC miss 6 O no Ox00003008 Ox00003 Ох10000 miss 3 Ох10000008 1 yes Ox00005958 OX0000300C Ox00001080 OX00007F68...
Question 30 7 pts Consider a computer system that uses virtual memory with paging with a TUB. Suppose main memory access time is 10 ns and the time to look up the TLB 1 ns. Assume no page faults and the TLB has a hit of 95%. What is the effective memory access time (express in ns)
Computer
architecture
rence1 (Choone) D Question 21 Regarding the virtual memory system, check all the statements that are true. Each program has its own page table, A program's memory space must be a contiguous physical addresses in the RAM, The user program is responsible for maintaining its own page table, If a computer has 1 GB RAM, the software can be written to use 2 GB of memory. It enables multiple programs to share the computer's memory, each program can...
As described in 5.7, virtual memory uses a page table to track the mapping of virtual addresses to the physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitutes a stream of virtual addresses as seen on a system. Assume 4 KiB pages, a 4-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. 4669, 2227, 13916, 34587, 48870,...
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Consider the following system: Byte addressable 16-bit addresses 256B pages Single level Page Table System The system utilizes a fully-associative TLB with 4 entries and an LRU replacement policy. Given the access pattern and timings below, complete the following table. Assume the TLB begins initially empty and the cache is physically addressed NOTE: Access times are not inclusive and components are accessed sequentially. Time to update the TLB is negligible, everything else that needs to be updated will require a...
2. A computer uses virtual memory implemented by paging. The TLB lookup takes 150 ns and the update takes 300 ns. The PT lookup takes 2 us and the update takes 4 us. Loading a word from main memory onto the CPU takes 25 us and loading a page from the disk into main memory takes 20 ms. The TLB hit ratio is 0.3 and the main memory hit ratio is 0.4. Compute the average access time for a referenced...
please answer
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