Question

As described in 5.7, virtual memory uses a page table to track the mapping of virtual addresses to the physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitutes a stream of virtual addresses as seen on a system. Assume 4 KiB pages, a 4-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. 4669, 2227, 13916, 34587, 48870, 12608, 49225 Given the address stream shown, and the initial TLB and page tables states provided above, show the final state of the system. Also list for each reference if it is a hit in the TLB, a hit in the page table, or a page fault. Repeat 5.11.1, but this time use 16 KiB pages instead of 4 KiB pages. What would some of the advantages of having a larger page size? What are some disadvantages?

Answer 1

5.11.1) Consider a 4-entry fully associative TLB. The number of pages is 4 KiB. TLB (Translation lookaside buffer) is the subset for the associative mapping of virtual number and the physical number. Consider the following Virtual address stream that are to be referenced: 4669, 2227, 13916, 34587, 48870, 12608, 49225 Consider the initial TLB as follows: Valid Bit | Tag or Virtual Physical Page Number Number 11 12 0 4

The page table is as follows: Index Valid Bit 0 Physical Page or In Disk 5 Disk Disk 0 0 2 5 6 8 9 10 11 0 1 0 0 1 1 Diski 4 Diski Disk 3 12 Need to calculate the final state of the system and the list for each reference if it is hit or page fault. To calculate the new entry, convert the virtual address into 32-bit binary number. The Binary equivalent values of the virtual addresses are divided into page number and page offset. As page size is 4 KiB =212 bytes, the least significant 12 bits indicate page offset and the remaining (32-12) =20 bits indicate the page number.

The virtual page numbers of the addresses are shown in the below table: Virtual address (in binary) Virtual page Number (in decimal) Virtual address (in decimal) 4669 2227 13916 34587 48870 12608 49225 0000 0000 0000 0000 0001 0010 0011 1101 0000 0000 0000 0000 0000 1000 1011 0011 0000 0000 0000 0000 0011 0110 0101 1100 0000 0000 0000 0000 1000 0111 0001 1011 0000 0000 0000 0000 1011 1110 1110 0110 0000 0000 0000 0000 0011 0001 0100 0000 0000 0000 0000 0000 1100 0000 0100 1001 8 • • • If the virtual page number of each address is present the tag value of the TLB table, then the reference address is TLB hit. If it is not present in TLB table, the page table need to be checked. If the page number is having a valid bit 1, then it is a TLB miss. If the page number is having a valid bit 0, then it is a Page fault. The below table shows the list for each reference if it is hit or page fault. Virtual address 4669 2227 13916 34587 48870 12608 49225 Hit/Miss/ Page fault Page Fault Miss Hit Page Fault Page Fault Hit Page Fault

The value of LRU is provided in the initial TLB table. To get the LRU value, provide lowest value to the tag which is having valid bit 0 and highest value to the tag which is present in TLB table. Other values can be provided in sequence. When page fault or miss occurs, the value having least LRU value is replaced as that tag is provide highest LRU. Values of LRU in other tags are changed simultaneously. Then, the TLB table when address 4669 arrives is, Valid Bit LRU Tag or Virtual Number 11 1 Physical Number 12 4 6 13 1 3 3

When address 2227 arrives is, Valid Bit LRU Tag or Virtual Number 11 Physical Number 12 1 2 1 3 1 6 13 1 3 L When address 13916 arrives is, Valid Bit LRU Tag or Virtual Number 11 Physical Number 12 1 1 1 3 1 6 132 4 When address 34587 arrives is, Valid Bit LRU Tag or Virtual Number Physical Number 14 5 6 13

When address 48870 arrives is, Valid Bit LRU Tag or Virtual Number Physical Number 14 1 1 0 3 11 5 6 12 3 1 2 4 When address 12608 arrives is, LRU Physical Number Valid Bit Tag or Virtual Number 18 1 0 14 1 11 12 3 When address 49225 arrives is, LRU Valid Bit | Tag or Virtual Number Physical Number 14 1 12 15

Therefore, the final TLB table when page size is 4 KiB is shown below: LRU Physical Number 14 Valid Bit | Tag or Virtual Number 18 1 12 1 3 11 15 6 12 4 3 2 After inserting the values in page table, the final page table structure is changed as shown in the following table: Index 0 1 2 3 4 5 6 Valid Bit 1 1 0 1 1 1 0 Physical Number or In Disk 5 13 Disk 6 9 11 Disk 8 10 11 12 14 Disk 3 12 15 1 1

5.11.2) Consider a 4-entry fully associative TLB with true LRU replacement. The number of pages is 16 KiB. Consider the following Virtual address stream that are to be referenced: 4669, 2227, 13916, 34587, 48870, 12608, 49225 Initial TLB: Valid Bit Tag or Virtual Number 11 Physical Number 12 0 4 9

Initial Page table: Index Valid Bit 2 3 4 0 0 1 Physical Number or In Disk 5 Disk Disk 6 9 11 Disk 4 Disk Disk 3 12 0 8 0 90 10 1 11 Need to calculate the final state of the system and the list for each reference if it is hit or page fault. To calculate the new entry, convert the virtual address into 32-bit binary number. The Binary equivalent values of the virtual addresses are divided into page number and page offset. As page size is 16 KiB =214 bytes, the least significant 14 bits indicate page offset and the remaining (32-14) =18 bits indicate the page number.

The virtual page numbers of the addresses are shown in the below table: Virtual address (in decimal) Virtual address (in binary) Page number (in decimal) 4669 0000 0000 0000 0000 0001 0010 0011 1101 2227 0000 0000 0000 0000 0000 1000 1011 0011 0 13916 0000 0000 0000 0000 0011 0110 0101 1100 0000 0000 0000 0000 1000 0111 0001 1011 34587 48870 12608 0000 0000 0000 0000 1011 1110 1110 0110 0000 0000 0000 0000 0011 0001 0100 0000 0000 0000 0000 0000 1100 0000 0100 1001 49225 If the virtual page number of each address is present the tag value of the TLB table, then the reference address is TLB hit. If it is not present in TLB table, the page table need to be checked. If the page number is having a valid bit 1, then it is a TLB miss. If the page number is having a valid bit 0, then it is a Page fault. For true LRU policy in TLB, LRU-priorities to the TLB entries are given. • •

The following table gives the hit or page fault list for new entries: Hit Virtual address Hit/Miss/ Page fault 4669 Miss 2227 13916 Hit 34587 Page Fault 48870 Hit 12608 Hit 49225 Hit Assumption: Here, TLB entry with valid-bit 0 is given lowest priority, while TLB entry with tag 3 is given highest priority because page table index 3 is being accessed in future reference strings. So, the updated TLB table when address 4669 arrives is: Valid Bit | Tag or Virtual Number 11 LRU- priorities Physical Number 12 4 1 3

When address 2227 arrives is: Valid Bit LRU- priorities Tag or Virtual Number 11 7 Physical Number 12 4 1 1 2 When address 13916 arrives is: Valid Bit Tag or Virtual Number 11 Physical Number LRU- priorities 1 12 1 3 6 3 When address 34587 arrives is: Valid Bit Tag or Virtual Number Physical Number LRU- priorities 13 4

When address 48870 arrives is: LRU- priorities Valid Bit Tag or Virtual Physical Number Number 12 13 1 7 14 i 0 5 3 When address 12608 arrives is: Valid Bit Tag or Virtual Physical Number Number 12 13 LRU- priorities 3 6 2 1 1 L 0 5 When address 49225 arrives is: Valid Bit Tag or Virtual Number 2 LRU- priorities Physical Number 13 4 1 7

Therefore, the final TLB table when page size is 16 KiB is shown below: Valid Bit LRU- priorities 2 1 1 1 1 Tag or Virtual Number 2 7 3 0 Physical Number 13 4 6 5 L 4 3 After inserting the values in page table, the final page table structure is changed as shown in the following table: Valid Bit Physical Number or In Disk Disk 13 1 L 1 9 11 Disk 0 Disk Disk O 0 i 1 0 0 12 Disk Disk

The advantages of having larger page size16 KiB on 4 KiB: • • • If the page increase, the number of page faults and the miss rate decreases. The searching time in the page table is reduced. The size of the page tables will be reduced. The disadvantages of using page size 16 KiB on 4 KiB: • If the page size increase, it leads to higher fragmentation. Because of using the same page number for different addresses, more fragments will generate. • Utilization of physical memory becomes too less which results in inefficiency of memory usage. • If there is no locality in the higher page size, more page faults will occur.