Question

1) Given a virtual memory system with: virtual address 36 bits physical address 32 bits 32KB pages (15 bit page offset) Each page table entry has bits for valid, execute, read and dirty (4 bits total) and bits for a physical page number.

a) How many bits in the page table? (do not answer in bytes!) Three digit accuracy is good enough. The exponent may be either a power of 2 or a power of 10.

b) The virtual address is extended to 38 bits, all else stays the same. How many bits in the page table? (do not answer in bytes!) Three digit accuracy is good enough. The exponent may be either a power of 2 or a power of 10. Note: There will be a page table for every process that is running, yet the page tables are typically not completely allocated. Only the sections of the page table being used are typically populated.

c) A fully associative TLB that has 32 blocks, 1 entry per block, is needed for the page table like a) VA=35, PA=32, PO=15. The TLB must hold a page table entry and a tag in each block. How many bits in the TLB? (do not answer in bytes!)

d) Draw a two way associative TLB that has 4 blocks, 8 total PPN's, for the page table a) Virtual address 35 bits, physical address 32 bits, offset 15 bits, 4 bits V,E,R,D. See lecture 21 for 4 way associative cash, you only use 2. The top will be the virtual address with the virtual page number and virtual page offset. The bottom will be the physical address with the physical page number and physical page offset. Show the detail of all fields, connections, mux, comparators. Label the width of all fields and signals. Refer to the textbook or class lecture notes for sample TLB's. If you send EMail, make sure it prints in 80 column fixed width font.

Answer 1

a)

Page offset = 15 bits (given)

Physical Page Number (PPN) = Phusical address bits - page offset

= 32-15

= 17 bits

Page Table Entry (PTE) = PPN + valid Bits/Protection bits

= 17+4 = 21

number of page entries = Virtual address - offset

  = 36-17

= 19 bits, we need 2^19 entries to represent the full range of the virtual addresses.

So the total page table size comes up to 2^19 * 21 bits

b)

number of page entries = Virtual address - offset

  = 38-17

= 21 bits, we need 2^21 entries to represent the full range of the virtual addresses.

So the total page table size comes up to 2^21 * 21 bits

c)

TLB offset = 0 (TLBs have no offset! An entry is a page number)

TLB index= 2 bits

TLB tag= = 35 –2 = 33 bits

Entry size = size of Phys Page Num = 32 bits