Homework Answers
Per policy, I can answer only one question at a time. Solution
to your first question is given below. First we will calculate the
execution time for 2M instructions for both CPUs respectively. CPU
with higher value of MIPS must be selected.
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CASE II AziTech is considering the design of a new CPU for its new model of...
AziTech is considering the design of a new CPU for its new model of computer systems...
AziTech is considering the design of a new CPU for its new model of computer systems for 2021. It is considering choosing between two (2) CPU (CPUA and CPUB) implementations based on their performance. Both CPU are expected to have the same instruction set architecture. CPUA has a clock cycle time of 60 ns and CPUB has a clock cycle time of 75 ns. The same number of a particular instruction type is expected to be executed on both CPUs...
20 pts] 2- Consider the internal structure of the pseudo-CPU discussed in class augmented with a...
20 pts] 2- Consider the internal structure of the pseudo-CPU discussed in class augmented with a single-port register file (i.e., only one register value can be read at a time) containing 32 8-bit registers (RO-R31) and a Stack Pointer (SP). Suppose the pseudo-CPU can be used to implement the AVR instruction ICALL (Indirect Call to Subroutine) with the format shown below: 10001 10101 00001 10011 ICALL pushes the return address onto the stack and jumps to the 16-bit target address...
Page 2 SECTIONA (a) To improve the performance of a computer, a new design aims to raise the overall system speed by 1.5 times of the original version It is known that the system performance effi...
Page 2 SECTIONA (a) To improve the performance of a computer, a new design aims to raise the overall system speed by 1.5 times of the original version It is known that the system performance efficiency is contributed to by both CPU (40%) and memory (60%). In the new design, only the CPU can be changed By using Amdahl's law, calculate how much faster the new CPU must perform to meet the overall speed-up requirement. (6 marks) b) In the...
Design and implement a C Language program that measures the performance of given processors. There are...
Design and implement a C Language program that measures the
performance of given processors.
There are several metrics that measure the performance of a
processor. We will be using the following 3 measures:
1.CPI (clock cycles per instruction) = #clock cycles
/#instructions
2.CPU execution time = #instructions x CPI x clock cycle time
.
cylce time = 1/CPU clock rate in hertz units
3.MIPS (mega instructions per second)= #instrucrions/ CPU X
1000000
Typically, processors’ performance is measured using a wide...
1. (6 Marks) Using the single bus architecture provided below (as seen in class also), write the ...
1. (6 Marks) Using the single bus architecture provided below (as seen in class also), write the sequence of micro-code instructions for doing the following tasks (as given by points a), b) and c)). You do not have to worry about timing in this question. For memory reads/writes, assume the operation finishes in 1 clock cyclıe (no timing issues). For each micro-code you provide, comment on what you are accomplishing The following table gives ALU functions operating on numbers in...
I need help with 2,3,4 please 1. Design a sequential circuit for a vending machine controller...
I need help with 2,3,4 please
1. Design a sequential circuit for a vending machine controller where a product sells for 30 cents, and the machine takes quarters, and dimes only. It also releases 5 cents, 15 cents and 20 cents for changes. Show the complete design using D-FFs including the Transition Diagram, Transition Table and combinational circuits. 2. Carry out a step by step procedure of Booth algorithm in multiplying the two 6-bit2's complement numbers: a. Multiplicand: 010011 Multiplier:...
26. The is a group of bits that tells the computer to perform a specific operation...
26. The is a group of bits that tells the computer to perform a specific operation A). program counter B). Opcode C). register D). microoperation 27. A condition called occurs in unsigned binary representation of a number when the result of an arithmetic operation is outside the range of allowable precision for the given number of bits. A). underflow B). 2's complement C). overflow D) bitwise complement 28. An iteration of the fetch-decode-execute cycle includes which of the following events?...
Consider a standard 5-stage MIPS pipeline of the type discussed during the class sessions: IF- ID-EX-M-WB....
Consider a standard 5-stage MIPS pipeline of the type discussed
during the class sessions: IF-
ID-EX-M-WB.
Assume that forwarding is not implemented and only the hazard
detection and stall logic is
implemented so that all data dependencies are handled by having the
pipeline stall until the
register fetch will result in the correct data being fetched.
Furthermore, assume that the memory is written/updated in the first
half of the clock cycle
(i.e. on the rising edge of the clock) and...
3. Finite State Machine. Using a ROM based finite state machine (FSM), design a bi-directional repetitive...
3. Finite State Machine. Using a ROM based finite state machine (FSM), design a bi-directional repetitive 3-bit modulo-6 (0,1,2,3,4,5) counter (see Table 3). The design has one input named Dir and three outputs named B2, B1 and BO. The outputs (B2, B1 and BO) are dependent upon being in the present state only. After each clock pulse, when Dir is at logic "O', the outputs (B2, B1, BO) step through the count sequence in following order:- 0,1,2,3,4,5. After each clock...
20 pts] 2- Consider the internal structure of the pseudo-CPU discussed in class augmented with a single-port register file (i.e., only one register value can be read at a time) containing 32 8-bit registers (RO-R31) and a Stack Pointer (SP). Suppose the pseudo-CPU can be used to implement the AVR instruction ICALL (Indirect Call to Subroutine) with the format shown below: 10001 10101 00001 10011 ICALL pushes the return address onto the stack and jumps to the 16-bit target address...
Page 2 SECTIONA (a) To improve the performance of a computer, a new design aims to raise the overall system speed by 1.5 times of the original version It is known that the system performance efficiency is contributed to by both CPU (40%) and memory (60%). In the new design, only the CPU can be changed By using Amdahl's law, calculate how much faster the new CPU must perform to meet the overall speed-up requirement. (6 marks) b) In the...
Design and implement a C Language program that measures the
performance of given processors.
There are several metrics that measure the performance of a
processor. We will be using the following 3 measures:
1.CPI (clock cycles per instruction) = #clock cycles
/#instructions
2.CPU execution time = #instructions x CPI x clock cycle time
.
cylce time = 1/CPU clock rate in hertz units
3.MIPS (mega instructions per second)= #instrucrions/ CPU X
1000000
Typically, processors’ performance is measured using a wide...
1. (6 Marks) Using the single bus architecture provided below (as seen in class also), write the sequence of micro-code instructions for doing the following tasks (as given by points a), b) and c)). You do not have to worry about timing in this question. For memory reads/writes, assume the operation finishes in 1 clock cyclıe (no timing issues). For each micro-code you provide, comment on what you are accomplishing The following table gives ALU functions operating on numbers in...
I need help with 2,3,4 please
1. Design a sequential circuit for a vending machine controller where a product sells for 30 cents, and the machine takes quarters, and dimes only. It also releases 5 cents, 15 cents and 20 cents for changes. Show the complete design using D-FFs including the Transition Diagram, Transition Table and combinational circuits. 2. Carry out a step by step procedure of Booth algorithm in multiplying the two 6-bit2's complement numbers: a. Multiplicand: 010011 Multiplier:...
26. The is a group of bits that tells the computer to perform a specific operation A). program counter B). Opcode C). register D). microoperation 27. A condition called occurs in unsigned binary representation of a number when the result of an arithmetic operation is outside the range of allowable precision for the given number of bits. A). underflow B). 2's complement C). overflow D) bitwise complement 28. An iteration of the fetch-decode-execute cycle includes which of the following events?...
Consider a standard 5-stage MIPS pipeline of the type discussed
during the class sessions: IF-
ID-EX-M-WB.
Assume that forwarding is not implemented and only the hazard
detection and stall logic is
implemented so that all data dependencies are handled by having the
pipeline stall until the
register fetch will result in the correct data being fetched.
Furthermore, assume that the memory is written/updated in the first
half of the clock cycle
(i.e. on the rising edge of the clock) and...
3. Finite State Machine. Using a ROM based finite state machine (FSM), design a bi-directional repetitive 3-bit modulo-6 (0,1,2,3,4,5) counter (see Table 3). The design has one input named Dir and three outputs named B2, B1 and BO. The outputs (B2, B1 and BO) are dependent upon being in the present state only. After each clock pulse, when Dir is at logic "O', the outputs (B2, B1, BO) step through the count sequence in following order:- 0,1,2,3,4,5. After each clock...
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