Question

A non-pipelined processor has a clock rate of 1 GHz and an average instruction takes 9 cycles to execute. The manufacturer has decided to design a pipelined version of this processor. For this purpose, the instruction cycle has been divided into five stages with the following latencies: Stage 1 – 2.0 ns,Stage 2 – 1.5 ns, Stage 3 – 1.0 ns, Stage 4 – 2.6 ns, Stage 5 – 1.9 ns. Each stage will require an extra 0.4 ns for the buffers between the pipeline stages, including the last stage.

1. a) What clock cycle time will be required for the pipelined processor? What will be the corresponding clock rate?

2. b) What will be the execution time for a single instruction in the pipelined processor? What is the percentage increase compared to the non-pipelined processor?

3. c) What is the maximum throughput of the pipelined processor expressed as MIPS? What is the speedup over the non-pipelined processor?

Answer 1

given that clock rate = 1GHZ = 10^9 HZ means 1 clock time = 1/ 10^9 second = 1nanosecond

given that non pipelined take 9 cycle means non pipeline take 9* 1nanosecond = 9 nanoesecond to excute a instruction.

1) since there is no specific clock rate gien for pipelined processor

so clock cycle time remain same for pipeline as non pipeline

similarly clock rate is remain same for pipeline as non pipeline

so clock cycle time = 1nanoseocnd for pipeline and non pipeline both

and clock rate = 1GHZ for pipeline and non pipeline

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2)

a pipeline version of this processor has 5 stege with time = 2.0 ns, 1,5ns, 1.0ns , 2.6ns, 1.9ns

each stage require 0.4ns extra for buffer

so effective time of 5 stage = 2.4ns , 1.9ns, 1.4ns , 3ns, 2.3ns

in pipeline all stage operate in parallel so overall time to take execute 1 instruction = maximum of all 5 stage time

= max { 2.4, 1.9, 1.4, 3.0 ,2.3 } = 3nanosecond

so execution time for single instruction in pipeline processor = 3nanosecond

It is 3 times faster than non pipelined processor .so it take only 33.33% time as compared to non pipeline faster .

so it is 300% time faster than non pipelin processor .

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3)

speed up = time taken to execute 1 instruction in non pipeline manner /   time taken to execute 1 instruction in non pipeline manner

speed up = 9/3 = 3

so speed up over the non-pipelined processor = 3

Ideally speed up = number of stage = 5

so throughput = practically achieved speed up / Ideally speed up

= 3/5 = 0.6

= 60%

  the maximum throughput of the pipelined processor expressed as MIPS is 60%