Question

High level sysntheis data flow graph scheduling

For this problem, consider the DFG given below. Unless otherwise indicated, assume that all arithmetic-logical operations are executed by ALU and the multiplication operation is executed by the multiplier. a. Assuming two ALUs and two multiplications units are available and each operation takes 1 clock cycle to execute, schedule the operations to find the minimum latency. b. Assuming two ALUs and two multiplications units are available and ALU operation takes 1 clock cycle and multiplication operation takes 2 clock cycles to execute, schedule the operations to find the minimum latency.

Answer 1

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in Oo 노the &f o.1 3

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