Question

Please help me complete all these questions ( Question 1-10)

1 -3) Complete the truth tables below. 10 10 1 11 8) For the D Flip-Flop in Figure 1, draw the output waveform for the inputs shown. Assume Q is initially 0.Assume Q starts low. > - 9) For the D Flip-Flop in Figure 2, draw the output waveform for the inputs shown. Assume Q starts low. (Hint - The FF in figure 1 is NOT identical to the FF in figure 2) - ea t ejo Figure 1 Figure 2 10) Draw the output waveforms for the circuit to the right taking into account the gate delays. delbero > 10 ko DIDA AND, OR, & NOR gates have a 20ns delay and Inverters have a 10 ns delay. 10ns

Answer 1

Qnti El Ř I anti Indeterminalle - 0 To o an - Indeterminate anti Qanti = Output of flipflop after clock occurance an = Output of flipflop before clock occurance * In short an is previous state, ant is next state 8) It is positive edge triggered flipflop. When ever positive edge is triggered, the output will change according to input. *Hence clock toggering is very importast. (positive edge) (Negative edge)

Here it may be either bort we cannot determine it. x there D flip flopis negative edge triggered thpflop.so, whenever negative edge occurs, output stage changes

5% Eloka Aol=A : Lations delay Azarted B=A+ delay <2005 c = B + delay 40nst