Question

Please ignore the writing. Explain steps.

EE 301 DESIGN Due Morch 5 PROBLEM problem! Design a Right shift Register using four DIES with clock enable four to 1 mux, and a single or gale Series ACLK 7 CLK PRC CLK-

Answer 1

The right-shift register circuit using four D flip-flops with clock enable, four 2-to-1 MUXs and a single OR gate.

Doho pohd HD eh Me HD 2. so CE DACE BITED. ICE CLK Figure 1

Explanation:

The shift register has two control inputs, shift enable(sh) and load enable(ld).

If sh = 1 and clocking the register causes the serial input (SI) to be shifted into the first flip-flop, the data in flip-flops Q3,Q2 and Q1 are shifted right.
So, the (Clock Enable) CE = sh + ld.

Note: If you have any doubts feel free to comment.