
*For a clearer view of the datapath*

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Answer choices for all
instruction : andi $t0, $t1, 4
control signals
RegDst = 1
Jump = 0
Branch = 0
MemRead = 0
MemtoReg = 0
ALUOp = 000
MemWrite = 0
ALUSrc = 1
RegWrite = 1
RegDst = 0
Jump = 0
Branch = 0
MemRead = 0
MemtoReg = 0
ALUOp = and
MemWrite = 0
ALUSrc = 1
RegWrite = 1
Reasoning:
The instruction we are determining control signals for is:
andi $t0, $t1, 4
This is And Immediate, an arithmetic I-Type. Since this is not a jump or a branch, we can set both of those signals to 0:
Jump = 0
Branch = 0
Since this is not a lw (load word), we set both memread and memtoreg to 0:
MemRead = 0
MemtoReg = 0
Since this is not a sw (store word), we set memwrite to 0:
MemWrite = 0
This leaves Register Destination, ALU Operations, ALU Source, and Register Write. The And Immediate instruction needs to perform an AND operation on one register and the immediate field, and store the result in the register file. To store a result in the register file, we set Register Write to 1:
RegWrite = 1
To store the result into the correct register, we select the bits in the instruction associated with the destination register for I-Types. These are bits [20-16] and they are associated with a RegDst signal of 0:
RegDst = 0
To ensure the second parameter to the ALU is the immediate value, we set ALU Source to 1:
ALUSrc = 1
Finally, we will tell the ALU to perform an AND operation.
ALUOp = and
*For a clearer view of the datapath* Answer choices for all Consider the MIPS single cycle...
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it is the same question
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