Answer-
initially present state of all flip-flop is 0.
and at load all input time, CLK is 1.
| CLK | Data In | FFA(QA) | FFB(QB) | FFC(QC) | FFD(QD)=Data out |
| Initial | 0 | 0 | 0 | 0 | |
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0 | 0 | 0 | 0 | 0 |
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1 | 1 | 0 | 0 | 0 |
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1 | 1 | 1 | 0 | 0 |
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0 | 0 | 1 | 1 | 0 |
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1 | 1 | 0 | 1 | 1 |
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0 | 0 | 1 | 0 | 1 |
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0 | 0 | 0 | 1 | 0 |
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1 | 1 | 0 | 0 | 1 |
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1 | 1 | 1 | 0 | 0 |
| CLK | Serial Data In | Serial Data Out |
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0 | 0 |
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1 | 0 |
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1 | 0 |
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0 | 0 |
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1 | 1 |
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0 | 1 |
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0 | 0 |
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1 | 1 |
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1 | 0 |
my bread board broke and i need the data output. 38 Make modifications to your circuit...
I really need help with these two questions. I posted
earlier but I didn't get any assistance. please help
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Can someone please show me a circuit diagram so i can see how to
construct this on a bread board i am id 6 yhanks in advance
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