Question

I really need help with these two questions. I posted earlier but I didn't get any assistance. please help

The shift register below has shift, load and clock inputs as shown. The serial data input is tied 3) High (1). The state of the data input lines is indicated. Determine the data out waveform in reference to the clock pulses.ope) D, D. 0 0 SHIFT/LOAD SRG 4 Serial Data In Data Ost CLK CLK SH/LD Serial data Out Show a complete timing diagram for a 3-bit, positive edge triggered, Active High Up/Active Low Down, counter that goes through the following sequence: 0, 1, 2, 1,0, 1,2,3,4, 5,6, 7,0, 1,0,1. (20pts) CLK CTEN D /U Q 0 Q 1 Q 2

Answer 1

Data ut Ve ederigecrrd negisteg e s hiph

Let fag 3-bi qSo having amre and G, aj LSB fosiven quent o,12,,0,1,2, 3, 4, 5,4, ,0,1,0. CTEN n/a