Consider a machine, which has a clock rate of 210 MHz. The following measurements are recorded...
Consider a machine, which has a clock rate of 210 MHz. The following measurements are recorded on the machine running a given set of benchmark programs. Determine the effective CPI, MIPS rate, and execution time for the machine
| Instruction type | Instruction count Millions | CPI |
|---|---|---|
| Arithmetic and logic | 6 | 2 |
| Load and store | 3 | 3 |
| Branch | 2 | 6 |
| Others | 4 | 3 |
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Consider a machine, which has a clock rate of 210 MHz. The
following measurements are recorded...
c. Performance: Company A's processor and Company B's processor are benchmarked on the same program. The...
c. Performance: Company A's processor and Company B's processor are benchmarked on the same program. The CPI of the component instructions that are executed in the program are shown above for each processor. Additionally, the number of instructions of each type is provided. Company A 5 Branch CPI Load/Store CPI Arithmetic CPI 7 1 Company B 4 Branch CPI Load/Store CPI Arithmetic CPI 9 1 Program Instruction Count Branch Load/Store Arithmetic CPL 1.2x109 1.67x1010 1.5x1011 i. Assume Company A has...
Problem 1 Assume that a processor with a clock rate of 1 GHz clock runs a...
Problem 1 Assume that a processor with a clock rate of 1 GHz clock runs a benchmark program w mix of instructions given in the table below. Instruction class CPI FP INT Load/Store (L/S) Branch Instruction count 50 x 106 110 x 106 50 x 106 10 x 106 By how much must the CPI of L/S instructions be improved if the program is to run two times faster?
18. We have two types of machine as follows: Processor Clock Rate (MHz)PSat CPU time (see...
18. We have two types of machine as follows: Processor Clock Rate (MHz)PSat CPU time (see 12 x Machine A Machine B 25 Mache A requires 12 times longer than Machine B measured in CPU time. For example, a program takes 1 second in Machine B will take 12 seconds. 1) What is the relative size of the instruction count for the program running on the two machines? 2) What is the effective CPI for the two machines?
I need help solving both the questions below and it is 109 instructions. 1. On machine...
I need help solving both the questions below and it is 109 instructions. 1. On machine X with a 4GHz CPU, there is a mix of four types of instruction: Operation Type Frequency CPI Arithmetic 50% 1 Load 20% 5 Store 10% 3 Branch 20% 2 Suppose your program has 109 instructions, what is the total execution time? 2. On machine Y with a 1GHz CPU, a benchmark program consists of the following four types of instructions: Instruction Type Number...
(e) Suppose we measure the code for the same program from two different compilers and obtain the following data. Assume clock rate is 3GHz, which code sequence will execute faster according to ex...
(e) Suppose we measure the code for the same program from two different compilers and obtain the following data. Assume clock rate is 3GHz, which code sequence will execute faster according to execution time? or According to MIPS? By how much? (25 pts CPI for Instructions Code from Instruction Count (billions) CPI Compiler 1 Compiler 2 9 1 3
(e) Suppose we measure the code for the same program from two different compilers and obtain the following data. Assume clock...
A processor is designed such that the clock of the processor runs at 1 GHz. The following table gives the instruction frequencies for the benchmark and how many cycles each instruction takes. Inst...
A processor is designed such that the clock of the processor runs at 1 GHz. The following table gives the instruction frequencies for the benchmark and how many cycles each instruction takes. Instruction Type Frequency Cycles Load & Stores 25% 10 cycles Arithmetic Instructions 65% 6 cycles Branch instructions 10% 4 cycles (a) Calculate the CPI for the above benchmark. (b) Suppose the amount of registers are doubled, such that clock cycle time increases by 40%. What is the new...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which ar...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which are located in memory from address 0 through 15. Show the result of the MIPS instruction "lw Ss0,4(Sa0)" for machines in little-endian byte orders, where Sa0 4. Address Contents Address Contents 9b lb 2 4 6 10 b4 c5 12 13 14 15 3d 5f 70 7 8f (b) (10pts)Assume we have the following time, performance and architecture parameters in the specified units Ec-...
Assume that a processor has the following CPIs, arithmetic ops(1), load/store(12), branch instructions(5). Consider a program...
Assume that a processor has the following CPIs, arithmetic ops(1), load/store(12), branch instructions(5). Consider a program that requires 10^6 arithmetic ops, .5 ∗ 10^6 load/stores and .3 ∗ 10^6 branch instructions. Each processors has a clock frequency of 2Ghz. Assume that the program is parallelized to run over multiple cores, the number of arithmetic and load/store instructions is divided by .6*p, where p is the number of processors. The number of branch instructions remains the same in each processor. (2*5=10)...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which are located in memory from address 0 through 15. Show the result of the MIPS instruction "lw Ss0,4(Sa0)" for machines in little-endian byte orders, where Sa0 4. Address Contents Address Contents 9b lb 2 4 6 10 b4 c5 12 13 14 15 3d 5f 70 7 8f (b) (10pts)Assume we have the following time, performance and architecture parameters in the specified units Ec-...
Suppose this program is executed in a computer in which the clock rate for the processor is 1.6 MHz
Figure 1: each block gives the number of different types of instructionsConsider a program with the execution flow shown in Figure 1. There are in total 3 types of instructions used in this program: Type 1 (in-processor calculation): execution rate as 1 per clock cycle; Type 2 (memory access): each instruction takes 2 clock cycles for execution; Type 3 (loop control): each instruction takes 2 clock cycles for jump into the loop block or 3 clock cycles for jump to the block after...
c. Performance: Company A's processor and Company B's processor are benchmarked on the same program. The CPI of the component instructions that are executed in the program are shown above for each processor. Additionally, the number of instructions of each type is provided. Company A 5 Branch CPI Load/Store CPI Arithmetic CPI 7 1 Company B 4 Branch CPI Load/Store CPI Arithmetic CPI 9 1 Program Instruction Count Branch Load/Store Arithmetic CPL 1.2x109 1.67x1010 1.5x1011 i. Assume Company A has...
Problem 1 Assume that a processor with a clock rate of 1 GHz clock runs a benchmark program w mix of instructions given in the table below. Instruction class CPI FP INT Load/Store (L/S) Branch Instruction count 50 x 106 110 x 106 50 x 106 10 x 106 By how much must the CPI of L/S instructions be improved if the program is to run two times faster?
18. We have two types of machine as follows: Processor Clock Rate (MHz)PSat CPU time (see 12 x Machine A Machine B 25 Mache A requires 12 times longer than Machine B measured in CPU time. For example, a program takes 1 second in Machine B will take 12 seconds. 1) What is the relative size of the instruction count for the program running on the two machines? 2) What is the effective CPI for the two machines?
(e) Suppose we measure the code for the same program from two different compilers and obtain the following data. Assume clock rate is 3GHz, which code sequence will execute faster according to execution time? or According to MIPS? By how much? (25 pts CPI for Instructions Code from Instruction Count (billions) CPI Compiler 1 Compiler 2 9 1 3
(e) Suppose we measure the code for the same program from two different compilers and obtain the following data. Assume clock...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which are located in memory from address 0 through 15. Show the result of the MIPS instruction "lw Ss0,4(Sa0)" for machines in little-endian byte orders, where Sa0 4. Address Contents Address Contents 9b lb 2 4 6 10 b4 c5 12 13 14 15 3d 5f 70 7 8f (b) (10pts)Assume we have the following time, performance and architecture parameters in the specified units Ec-...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which are located in memory from address 0 through 15. Show the result of the MIPS instruction "lw Ss0,4(Sa0)" for machines in little-endian byte orders, where Sa0 4. Address Contents Address Contents 9b lb 2 4 6 10 b4 c5 12 13 14 15 3d 5f 70 7 8f (b) (10pts)Assume we have the following time, performance and architecture parameters in the specified units Ec-...
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