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E9.5 An integrated CMOS digital circuit can be repre sented by the Bode diagram shown in Figure E9.5. (a) Find the gain and phase margins of the circuit. (b) Estimate how much we would need to reduce the system gain (dB) to obtain a phase margin of 60. 50 9 20 10 1 kHz 10 kHz 100 kHz 10 MHz -20 0 -180 l kHz 10kHz 100 kHz 1 MHz 10 MHz Frequency (b) -360 FIGURE E9.5 CMOS circuit.

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