Question

Consider an L1 cache that has 8 sets, is direct-mapped (1-way), and supports a block size of 64 bytes. For the following memory access pattern (shown as byte addresses), show which accesses are hits and misses. For each hit, indicate the set that yields the hit. (30 points)
0, 48, 84, 32, 96, 360, 560, 48, 84, 600, 84, 48.

Answer 1

Answer:

Consider the following information from the question: Number of sets in the L1 cache 8 Block size = 64 bytes Memory access pattern is 0, 48, 84, 32, 96, 360, 560, 48, 84, 600, 84, 48 Block offset-10B264-б bits the number of sets is 8 therefore, the index size 23-3-bits Represent the given addresses in binary and write it in tag, index and offset form as given below:

Address Binary address Tag Index Offset Hit or miss Miss Hit 48 84 32 110000 010100 100000 100000 101000 110000 110000 010100 011000 010100 110000 110000 000001 010100 001 Miss Hit Hit Miss Miss Hit Hit Miss Hit Hit 100000 000001 100000 000101 101000 001000 110000 001 360 560 48 84 600 84 48 101 001 110000 000001 010100 001001 011000 000001 010100 001 001 001 001 110000

If the memory reference is found in the cache, it will be a hit otherwise it is miss. . The above table gives the hit or miss for each memory reference. It is determined by checking the matching bits in tag and index bits. As the cache is initially empty, the first address is always miss. . The tag and index bits of the address 48 are matched. Therefore, it is a hit. . The index of the address 84 doesn't match with the index of above two addresses. Therefore, it is a miss. . The index of the address 32 matched therefore, it is a miss. . The index of 96 is matched with the index of 84 therefore, it is a hit. . The index of 360 doesn't matched with the above index of the addresses therefore, it is a miss. . The index of the 560 is matched but the tag is not matched. Therefore, it is a miss. . The memory addresses 48 and 84 is already loaded in the cache. Therefore, it is a hit. . The index of 600 is matched but the tag is not matched. Therefore, it is a miss. . The memory addresses 84 and 48 is already loaded in the cache. Therefore, it is a hit. The total number of Hits are 7 and Miss are 5.

Set for the address 48: 48 110000 Hit 110000 Set for the address 32: 32 100000 Hit 100000 Set for the address 96: 000001 001 100000 Hit 100000 Set for the address 84: 000001 84 001 010100 Hit 010100