Question

Q4) De-Multiplexer

A demultiplexer is a device that forwards one single input signal to one of several analog or digital output lines. A multiplexer of 2ⁿ outputs has n select lines, which are used to select which output line are used to relay to the input signal.

Please design the entity as well as the test bench for a 1-to-4 multiplexer. For this multiplexer, please use the following to refer to the inputs/outputs of the circuit: I0 as data input; S1 and S0 as selection inputs; and O0, O1, O2 and O3 as data outputs.

Your entity design is:

Your test bench design is:

In your test bench design, please enable each one of the 4 outputs at one time. For example enable the input signal In (low for 50ns, and then high for 50ns) to go through O0 first. Then, let this same input signal In (low for 50ns, and then high for 50ns) to go through O1, O2, and O3 correspondingly.

The result waveforms are:

Please select the signals to be simulated in the following order: S1, S0, In, O3, O2, O1, O0.

Answer 1

--VHDL Code

library ieee;
use ieee.std_logic_1164.all;

entity demultiplexer is
   port (   IO   : in std_logic;
       S1, S0   : in std_logic;
       O0, O1, O2, O3   : out std_logic
   );
end demultiplexer;

architecture arch of demultiplexer is

begin

O0 <= IO and (not S1) and (not S0);
O1 <= IO and (not S1) and S0;
O2 <= IO and S1 and (not S0);
O3 <= IO and S1 and S0;

end arch;

---------------------------------------------------------------------------------------------------------------------------------------------------------

--Testbench

library IEEE;
use IEEE.Std_logic_1164.all;

entity demultiplexer_tb is
end;

architecture bench of demultiplexer_tb is

component demultiplexer
   port (   IO   : in std_logic;
       S1, S0   : in std_logic;
       O0, O1, O2, O3   : out std_logic
   );
end component;

signal IO: std_logic;
signal S1, S0: std_logic;
signal O0, O1, O2, O3: std_logic ;

begin

uut: demultiplexer port map ( IO => IO,
S1 => S1,
S0 => S0,
O0 => O0,
O1 => O1,
O2 => O2,
O3 => O3 );

INPUT_IO: process
begin
  
IO <= '0';
wait for 50 ns;

IO <= '1';
wait for 50 ns;
end process;

SELECT_INPUT: process
begin
  
S1 <= '0';
S0 <= '0';
wait for 100 ns;

S1 <= '0';
S0 <= '1';
wait for 100 ns;

S1 <= '1';
S0 <= '0';
wait for 100 ns;

S1 <= '1';
S0 <= '1';
wait for 100 ns;

end process;

end;

--------------------------------------------------------------------------------------------------------------------------------------------------------

--Simulated on ModelSim

M ModelSim - INTEL FPGA STARTER EDITION 10.50 File Edit View Compile Simulate Add Transcript Tools Layout Bookmarks Window Help - X201EMO TO D LE . Search: Layout Simulate at Qault...+X Instance demultiplexer 100 pe O bjects = Name 1 10 21 E = +2x 20900000 per Wave - Default - INPUT_10 SELECT_IN standard texto std_logic_116- demultiplexer titolo fdemultiplexer_th/51 demultiplexer_tb/S01 fdemultiplexer tbC00 demultiplexer tb 01 0 fdemultiplexer_th/02 fdemultiplexer_th/03 Processes (Active) = Name =+2x Type (filtere 2010 Now Cursor 1 17877100000 ps 2 0900000 s 9345500000 9 396000000 ps - Wave - demultiplexer.vnd demultiplexer_tb.vnd nte: vim. WE Transcript Warning: (Van- SUN Cod not open u Using alternate file: /wlftaltany VSIM 5>run-all + Break key hit + Simulation stop requested. VSIM 6> VSIM 6> Now: 17,877,100 rs Delta: O demultiplexer_tb/s0 Type here to search O Bo e Mo @ BM A 6 3/9/20206