Question

Introduction Sequential logie circuits are circuits whose outputs depend not only on the present value of their input signals but also on the sequence of past inputs, the input history. Most sequential circuits we design are synchronous, or clocked. They use a rising or falling edge of a clock, or a level of an enable signal, to control their state or storage of data. For this project, you are required to design, implement, and test a PWM Generator, as well as a State Machine with Debounce. The design must show the use of 2 Buttons to control at least 10 PWM Duty Cycles and allow the Increase and Decrease of the duty cycle with the press of the respective button. This is your first joined group projeet please make sure you take the time to work through your problems as a team: Each member wl turn in the same copy of the assignment on blackboard. I will only need one physical copy of the report Recommended Design Procedure Find the number of input variables, the number of required output variables, and assign them meaningful names. 2.Create a truth table that detines a relationship between inputs and outputs. .Obtain a characteristic equation for each output. 4 Draw the logic diagram (you could use the diagram generated by your program). 5.Implement your design using VHDL 6.Test your design by creating a test bench 7.If possible, load your circuit to the board and test it (not required but could be agood practice- extra credit could be given).

Answer 1

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VHDL code:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY UNIVERSAL_SR IS

PORT(PIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

CLK,CLR: IN STD_LOGIC;

S:IN STD_LOGIC_VECTOR(1 DOWNTO 0);

DOUT:INOUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END UNIVERSAL_SR;

ARCHITECTURE BEHAVIORAL OF UNIVERSAL_SR IS

SIGNAL SR,SL:STD_LOGIC;

BEGIN PROCESS(CLK,CLR)

BEGIN IF(CLR='1') THEN

DOUT <= "0000";

ELSEIF(CLK'EVENT AND CLK='1') THEN

CASE S IS

WHEN "00" => DOUT <= DOUT;

WHEN "01" => DOUT <= SR & PIN(3 DOWNTO 1);

WHEN "10" => DOUT <= PIN(2 DOWNTO 0) & SL;

WHEN "11" => DOUT <= PIN;

WHEN OTHERS => DOUT <= "XXXX";

END CASE;

END IF;

END PROCESS;