Given This picture,
1. What is the subnet for the devices connected to IOU 1 and 2. What is the subnet for the devices connected to IOU 2.
Homework Answers
1. What is the subnet for the devices connected to IOU 1
Devices connected to IOU 1 are
192.168.1.21/26
192.168.1.22/26
Network Interface address is: 192.168.1.62/26
Here the network prefix is 26 so,take any address from the following subnet and convert to binary form and take its first 26 bits and remaining as zero’s then that will give the subnet id of that particular subnet
(where the network prefix is given in the address)
Binary equivalent of 192 is : 11000000
Binary equivalent of 168 is : 10101000
Binary equivalent of 1 is : 00000001
Binary equivalent of 21 is : 00010101
192.168.1.21 is : 11000000.10101000.00000001.00010101
take the first 26 bit and remaining as zeros
11000000.10101000.00000001.00000000 = 192.168.1.0
subnet id is : 192.168.1.0
Note: If you do this above operation with the address 192.168.1.62 or 192.168.1.22 also you will get same result, because both are also belongs to same subnet.
2. What is the subnet for the devices connected to IOU 2
Devices connected to IOU 2 are
192.168.1.103/26
192.168.1.104/26
Network interface address is : 192.168.1.126/26
Now we can to the operation with network interface address
Here the network prefix is 26 so,convert the address into binary form and take its first 26 bits and remaining as zero’s then that will give the subnet id of that particular subnet.
Binary equivalent of 192 is : 11000000
Binary equivalent of 168 is : 10101000
Binary equivalent of 1 is : 00000001
Binary equivalent of 126 is : 01111110
192.168.1.126 is: 11000000.10101000.00000001.01111110
take the first 26 bit and remaining as zeros
11000000.10101000.00000001.01000000 = 192.168.1.64
subnet id is : 192.168.1.64
Add Answer to:
Given This picture,
1. What is the subnet for the devices connected to IOU 1 and...
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using the information given below . what is the ip address , subnet mask , default...
using the information given below
. what is the ip address , subnet mask , default gateway?
** corrections
# of bits in subnet for A
:6
# of bits in submet for B:
3
PC-A
R1 G0/0
R GO/1
S1
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A block diagram of MIPS architecture is given below. What is the value of the control...
A block diagram of MIPS architecture is given below. What is the value of the control bit for each MUX during the execution of the given instruction? Note, you may use N/A if MUX output is not useful. > Add 2x MUX 4 ALU 4- Addresult Shift left 2 Instruction (31-26] RegDst Branch MemRead MemtoReg Control ALUOP MemWrite ALUSC RegWrite Instruction (25-21) PC Read address Instruction (20-16] Read register 1 Read Read data 1 register 2 Write Read MUX 2...
A block diagram of MIPS architecture is given below. What is the value of the control...
A block diagram of MIPS architecture is given below. What is the
value of the control bit for each MUX during the execution of the
given instruction? Note, you may use N/A if MUX output is not
useful.
Add MUX 4 ALU Addresult Shift left 2 RegDst Branch MemRead Instruction (31-26] MemtoReg Control ALUOp MemWrite ALUSrc RegWrite Instruction [25-21] PC Read address Read register 1 Read Read data 1 register 2 Write Read MUX 2 Zero Instruction (2016) MUX(1 Instruction...
it is the same question A block diagram of MIPS architecture is given below. What is...
it is the same question
A block diagram of MIPS architecture is given below. What is the value of the control bit for each MUX during the execution of the given instruction? Note, you may use N/Aif MUX output is not usefu Add MUX 4 ALU Add, result Shift left 2 RegDst Branch MemRead Instruction (31-26] Control Memto Reg ALUOP Mem Write ALUSrc RegWrite Instruction [25-21) PC Read address Instruction (20-16] MUXT Read register 1 Read Read data 1 register...
i cannot get all info in one picture so it is 2 pics Question 13 16...
i cannot get all info in one picture so it is 2 pics
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using the information given below
. what is the ip address , subnet mask , default gateway?
** corrections
# of bits in subnet for A
:6
# of bits in submet for B:
3
PC-A
R1 G0/0
R GO/1
S1
PC-B ?
assign the IP ADDRESS information with given information
Given, IP address: 202.44.66.0/24 For Subnet A: It needs 2 valid hosts 2 valid hosts + 2 (network and broadcast) = 22 i.e., It needs 2 bit as host...
Two ideal emf devices are connected to a set of resistors as
shown in the figure below. If E1 = 7.50 V, R1 = 12.00 ?, R2 = 4.50
?, R3 = 14.50 ?, R4 = 19.50 ?, and the current through R4 is 0.240
A, what is the emf E2?
4 1R
26
R1 E R2 R3 A 42 V battery is connected to a network of resistors with R1 40 2, R2 = 32 2, and R3 = 96 2. What is the equivalent resistance connected to the battery? (in Ohms) O 30.5 Ohms O 168 Ohms O 64.0 Ohms O 15.0 Ohms Submit Answer Tries 0/3 What is the potential difference across R3? (in V) O 15.8 V O 42.0 V 63.0 V O 31.5 V Submit Answer Tries 0/3
urgent
A block diagram of MIPS architecture is given below. What is the value of the control bit for each MUX during the execution of the given instruction. Note, you may use N/A if MUX output is not useful. >Add u MUX4 ALU 4 - Addresult Shift left 2) RegDst Branch MemRead Instruction (31-26) Control Memto Reg ALUOp MemWrite ALUSC RegWrite Instruction [25-21] PC Read address Instruction (20-16] Read register 1 Read Read data 1 register 2 Write Read MUX...
(5) In the circuit below, E1 11 V, E2 = 6 V, and E3 = 6 V. Also R1 26 a. R2 109 n, and R3 61 . Find the current through R1. E7 1. O 0.061 A 2.O 0.045 A 3. 0.026 A 4. O 0.034 A 5. O 0,083 A R2 E 3 E 1 W
A block diagram of MIPS architecture is given below. What is the value of the control bit for each MUX during the execution of the given instruction? Note, you may use N/A if MUX output is not useful. > Add 2x MUX 4 ALU 4- Addresult Shift left 2 Instruction (31-26] RegDst Branch MemRead MemtoReg Control ALUOP MemWrite ALUSC RegWrite Instruction (25-21) PC Read address Instruction (20-16] Read register 1 Read Read data 1 register 2 Write Read MUX 2...
A block diagram of MIPS architecture is given below. What is the
value of the control bit for each MUX during the execution of the
given instruction? Note, you may use N/A if MUX output is not
useful.
Add MUX 4 ALU Addresult Shift left 2 RegDst Branch MemRead Instruction (31-26] MemtoReg Control ALUOp MemWrite ALUSrc RegWrite Instruction [25-21] PC Read address Read register 1 Read Read data 1 register 2 Write Read MUX 2 Zero Instruction (2016) MUX(1 Instruction...
it is the same question
A block diagram of MIPS architecture is given below. What is the value of the control bit for each MUX during the execution of the given instruction? Note, you may use N/Aif MUX output is not usefu Add MUX 4 ALU Add, result Shift left 2 RegDst Branch MemRead Instruction (31-26] Control Memto Reg ALUOP Mem Write ALUSrc RegWrite Instruction [25-21) PC Read address Instruction (20-16] MUXT Read register 1 Read Read data 1 register...
i cannot get all info in one picture so it is 2 pics
Question 13 16 points A block acturing get you MUX4 Adid ALU re Rogo Branch SW Rent 2 Instruction 31-26 Contro MUSIC Pew ruction 25-29 Read 1 struction (2016 MUXI MUX 2 Zero ALULU MUX3 Instruction 1-0 Instruction memory Write Read con 15-11) Write data Register Gememory instruction (15-02 Sign22 extend ALU control Instruction 15-01 con 50 MUX 1 Instruction R1, 8(R2) MUX 2 MUX 3 ML...
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