Question

Verilog HDL

Design a logic module to multiply an 8-bit binary number A [0:7] by a 4-bit binary

number N [0:3]. The multiply is started when M is asserted. The output F is asserted

when the multiply is completed and the product P [0: 15] is available. The outputs need to

remain valid until the next multiply command is given. Assume M is valid for several of

your clock cycles and then is de-asserted.

Implement the multiply using repeated addition of A to form partial products.

Please also comment your code so I can understand

Answer 1

Module multiplier (clk, A, N, M, F, P): input clk: input [0: 7]A: input [0: 3]N: input M: output reg F: output reg [0: 15]P: reg [0: 3] Mplier: veg [0: 15] prodect: olusays @ (positive edge M) begin Mplier < = N: Product = 16 prime b0000000000000000: end alusays @ (posedge clk) begin if(M = = 1) begin if(Mplier 1 = 0) begin Mplier = Mplier - y: product = product + A: F = 0: else begin F = 1: rho = Product: end end and end module