Question

PROBLEM STATEMENT A logic circuit is needed to add multi-bit binary numbers. A 2-level circuit that would add two four-bit numbers would have 9 inputs and five outputs. Although a 2-level SOP or POS circuit theoretically would be very fast, it has numerous drawbacks that make it impractical. The design would be very complex in terms of the number of logic gates. The number of inputs for each gate would challenge target technologies. Testing would be difficult. In addition, this approach can not be extended easily to add binary numbers with a higher number of bits. Hierarchical design methods can be used instead to make simpler multilevel implementations with far fewer logic gates and wired connections. Simple building blocks or components are designed and tested, and then these blocks are used in the design of a larger circuit much in the same way as simple logic AND and OR gates are used. The cost of this simplification is a longer delay between an input level change and a valid output level. A full adder adds two one-bit numbers and also has a carry-in bit. The three-bit addition of the two inputs and the carry-in produces a sum output bit and a carry output bit. The three inputs are A and B and CIN, and the outputs SOUT and COUT To add multi-bit input values, full adders can be connected in sequence with the carry-out of one full adder connected to the carry-in of the next full adder. This is called a ripple carry adder. It is similar to adding decimal numbers on paper, a column at a time, and adding the carry out from each column to the next column to the left. An n-bit adder would use n full adders to create an n-bit sum and a carry out.

number 4 and 5 please!

Answer 1

O Giren that inputs for full adder is A,S, cin and output for full adder is Sout, Cout The truth table for full adder is A B Cin Sout I cout OD 0 0 oio 0 1 0.-öre 1 ---0-Coo Sout = 2 , +7) = A 8B 82 của Coat = ( 3,5,6,7) = AB+BC+AC 4) we have to write xexy verilog code for full adder creating the module name as myfulladd.

Vesilog code:- © module myfulladd (A, B, Cin, Sout, cout); Input A, B, Cin; output Sout, cont; assign Stuk= ABACin; assign cout = (A&B)/640)/C&A); end module. 5) we have to write verilog module for a two-bit ripple Carry adder named as myadderz. using two instances add module. verilny code:- module myadder 2 (A, B, Ciis, Sout, Cout); input (1:0] A, B; input cin; output (1:0) Sout; output cont, wire xl; myfulladd yi Calo), blo], Cin, s67, x1); my full add y2 [AC], 607, x1, SC ], Coutin endmodule.