Question

In quartus prime

1. Implement a 4-bit adder/subtractor using structural VHDL. The circuit will have two 4-bit data inputs (A and B), a control line (add /sub), a 4-bit sum output (S), a carry-out bit (Cout), and an overflow flag. You need two VHDL files (fulladd.vhd) and (hybrid.vhd) to implement the design. VHDL code, fulladd.vhd, will implement a single-bit full adder. The VHDL file, hybrid.vhd, will create four instances of the single-bit full adder. Four XOR gates will be needed to create the adder/subtractor. You also need another XOR gate to generate the overflow.

Devise a set of test input vectors (values) that will be used to verify that the circuit is working properly.

Answer 1

solution:

-- This is the XOR gate

library ieee;

use ieee.std_logic_1164.all;

--

entity xorGate is     

   port( A, B : in std_logic;

            F : out std_logic);

end xorGate;

--

architecture func of xorGate is

begin

   F <= A xor B;

end func;

--*============================

-- This is the NOT gate

library ieee;

use ieee.std_logic_1164.all;

--

entity NOTGATE is     

   port( A: in std_logic;

        F : out std_logic);

end NOTGATE;

--

architecture func of NOTGATE is

begin

   F <= not A;

end func;

--*============================

-- This is the FULL ADDER

library ieee;

use ieee.std_logic_1164.all;

--

entity fulladd is

   port( X, Y, Cin : in std_logic;

         sum, Cout : out std_logic);

end fulladd;

--Dataflow architecture.

--See Full Adder on Teahlab.com for structural version

architecture func of fulladd is

begin

   sum <= (X xor Y) xor Cin;

   Cout <= (X and (Y or Cin)) or (Cin and Y);

end func;

--*============================*============================

--Now we build the four bit Adder Subtractor

library ieee;

use ieee.std_logic_1164.all;

entity adderSubtractor is

   port( mode             : in std_logic;

          A3, A2, A1, A0 : in std_logic;

          B3, B2, B1, B0 : in std_logic;

          S3, S2, S1, S0 : out std_logic;

                  Cout, V : out std_logic);

end adderSubtractor;

--Structural architecture

architecture struct of adderSubtractor is

   component NOTGATE is             --NOT component

       port( A: in std_logic;

             F : out std_logic);

   end component;

   component xorGate is             --XOR component

       port( A, B : in std_logic;

                F : out std_logic);

   end component;

   component fulladd is                 --FULL ADDER component

      port( X, Y, Cin : in std_logic;

            sum, Cout : out std_logic);

   end component;

   --interconnecting wires

   signal C1, C2, C3, C4: std_logic; --intermediate carries

   signal n0, n1, n2, n3 : std_logic; --not outputs

begin

   GN0: NOTGATE port map(B0, n0);

   GN1: NOTGATE port map(B1, n1);

   GN2: NOTGATE port map(B2, n2);

   GN3: NOTGATE port map(B3, n3);

   FA0: fulladd port map(A0, n0, ‘1’, S0, C1); -- S0

   FA1: fulladd port map(A1, n1, C1, S1, C2); -- S1

   FA2: fulladd port map(A2, n2, C2, S2, C3); -- S2

   FA3: fulladd port map(A3, n3, C3, S3, C4); -- S3

   Vout: xorGate port map(C3, C4, V);                -- V

   Cout <= C4;                                       -- Cout

end struct;

----------------------------------------------------------END

----------------------------------------------------------END

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