Question

7. In a cache system we have the following attributes: 4 GB of DRAM 256 MB of physical memory space 2 MB of cache IKB per cache line Determine number of lines in cache. a) Determine the number of address bits out of the processor. b) c) Determine the number of bits needed for the block offset section of the address. If our cache is 8-way set associative, how many sets are there in the cache? d) How many bits are needed to select sets in this cache? e) Determine the number of bits of the tag, if 4-way set associative cache is implemented. f) Fill the table below with proper number of bits in each portion of the address bit map: g) Block Address # of bits needed to select each | set (from (d) above) Block Offset (Data Select) Tag

Answer 1

Solution

a)Determine number of lines in cache

in the questions, given

2 MB cache

1 KB per cache line

for easy calculation we will convert into 2 power

please note that

1 MB= 2 ²⁰

1 KB= 2 ¹⁰

Number of lines in cache

=cache/line

cache=2 MB= 2* 2 ²⁰

line= 1 KB= 2 ¹⁰

=2* 2 ²⁰/2 ¹⁰

=2 ²¹/2 ¹⁰

=2 ¹¹

=2048

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b) Determine the number of address bits out of the processor

Number of bits required to address all bytes in the largest memory given as per the question is

=256 MB

=256 * 2 ²⁰

=2 ⁸ * 2 ²⁰

= 2 ²⁸

so 28 bits is the answer

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c) Determine the number of bits needed for the block offset section of the address

Number of bits needed for the block offset section of the address

=size of the cache line

=1 KB

= 2 ¹⁰

=10 bits

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answered first 3 question, really sorry for that

please post remaining question separately, love to answer

all the best