Question

Explain the difference between a latch and an edge-triggered flip-flop – use timing diagrams in your explanation.

Answer 1

1. Both latches and flip-flops are circuit elements whose output depends not only on the present inputs, but also on previous inputs and outputs.

2. They both are hence referred as "sequential" elements.

3. Latches are level sensitive i.e. the output captures the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes.

4. Flip-Flops are edge sensitive i.e. flip flop will store the input only when there is a rising or falling edge of the clock.

5. A positive level latch is transparent to the positive level(enable), and it latches the final input before it is changing its level(i.e. before enable goes to '0' or before the clock goes to -ve level.)

6. A positive edge flop will have its output effective when the clock input changes from '0' to '1' state ('1' to '0' for negative edge flop) only.

In the above figure the waveforms are as follows.

1. Positive edge triggered flip flop

2. Negative edge triggered flip flop

3. Positive level sensitive Latch

4. Negative level sensitive Latch