Implement the function R = ab'h' + bch' + eg'h + fgh using *only* 2-to-1 multiplexers. Use the 2-to-1 multiplexer VHDL description from Problem 1 as a component to write VHDL code for the circuit design of function R. Perform CAD simulation of your design. (60)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_2to1 is
Port ( SEL : in STD_LOGIC;
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
Y : out std_logic);
end mux_2to1;
architecture Behavioral of mux_2to1 is
begin
Y <= I1 when (SEL = '1') else I0;
end Behavioral;
--------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity combinational_r is
Port ( a,b,c,e,f,g,h : in STD_LOGIC;
R : out std_logic);
end combinational_r;
architecture Behavioral of combinational_r is
component mux_2to1
Port ( SEL : in STD_LOGIC;
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
Y : out std_logic);
end component;
signal
nh,nbnh,cnh,ngh,gh,anbnh,bcnh,engh,fgh,s1,s2:std_logic;
begin
mux0: mux_2to1 port map(h,'1','0',nh);--h'
mux1: mux_2to1 port map(b,nh,'0',nbnh);--b'h'
mux2: mux_2to1 port map(h,c,'0',cnh);--ch'
mux3: mux_2to1 port map(g,h,'0',ngh);--g'h
mux4: mux_2to1 port map(g,'0',h,gh);--gh
mux5: mux_2to1 port map(a,'0',nbnh,anbnh);
mux6: mux_2to1 port map(b,'0',cnh,bcnh);
mux7: mux_2to1 port map(e,'0',ngh,engh);
mux8: mux_2to1 port map(f,'0',gh,fgh);
mux9: mux_2to1 port map(anbnh,bcnh,'1',s1);--ab'h'+bch'
mux10: mux_2to1 port map(engh,fgh,'1',s2);--eg'h'+fgh
mux11: mux_2to1 port map(s1,s2,'1',R);--R=ab'h'+bch'+eg'h'+fgh
end Behavioral;
-------------------------
--TESTBENCH:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity combinational_r_test is
end combinational_r_test;
architecture Behavioral of combinational_r_test is
component combinational_r
Port ( a,b,c,e,f,g,h : in STD_LOGIC;
R : out std_logic);
end component;
signal aa:std_logic_vector(6 downto 0);
signal RR:std_logic;
begin
uut: combinational_r port
map(a=>aa(6),b=>aa(5),c=>aa(4),e=>aa(3),f=>aa(2),g=>aa(1),h=>aa(0),R=>RR);
process
begin
for i in 0 to 127 loop
aa<=std_logic_vector(to_unsigned(i,7));
wait for 10ns;
end loop;
wait;
end process;
end Behavioral;
-------------------
RTL simulation:
aa6=a,aa5=b,aa4=c,aa3=e,aa2=f,aa1=g,aa0=h,RR=R
Implement the function R = ab'h' + bch' + eg'h + fgh using *only* 2-to-1 multiplexers....
ECE 275 - DIGITAL DESIGN Question 1: (@) Write VHDL code for a 2-to-1 multiplexer. - (6) Implement - using only the Sunction R= ab h + bch' + eg h + 8 h 2-to-1 multiplexers. Use the 2-to-1 multiplexer VHDL description as a component to write VHDL code for the of Sunction R, from Problem 1 circuit design
Use only 2-to-1 multiplexers to implement the circuit for the following function: F(A, B, C) = Pi M (1, 2, 4, 5) Assume the inverse of each input variable is available, (i.e., you can directly use the inverse of each input variable A, B, or C, in your answer.) Repeat P7, but this time using only one 4-to-1 multiplexer.
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