Question

(20 pts)VHDL. Implement the logic circuit specified in the following truth table by using a 4:1 mulitiplexer ome regular logic gates. 11 Draw a schematic of your implementation. 2) Suppose that you are given the following VHDL code of a 4:1 multiplexer. Please write a VHDL code to describe your implementation by using structure modeling technique, by using the following 4:1 multiplexer asia your answer component in your structure modeling. Note that you do not need to re-write the following 4:1 multiplexer code in entity mux4is portf do d1, d2, d3: in STD LOGIC s: in STD LOGICVECTOR(1 downto O); y: out STD. LOGIC) end entity architecture synth of mux4 is begin with s selecty e do when "oo: d1 when "01 d2 when "10 d3 when others; end;

Answer 1

1) Schematic

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2) VHDL CODE for 4x1 Mux using as an component in another top level entity

-- 4x1 mux code
library IEEE;
use IEEE.std_logic_1164.all;

entity mux4 is
port(d0,d1,d2,d3: in STD_LOGIC;
x : in STD_LOGIC_VECTOR(1 downto 0);
y : out STD_LOGIC
);
end entity;
architecture synth of mux4 is
begin
with x select y <=
d0 when "00",
d1 when "01",
d2 when "10",
d3 when others;
end;

-- Top Level Entity
-- In this top level entity we are using given 4x1 mux as a component
-- And giving it to D- Flip Flop input .

library IEEE;
use IEEE.std_logic_1164.all;

entity top is
port(rst,clk,d0,d1,d2,d3: in STD_LOGIC;
x : in STD_LOGIC_VECTOR(1 downto 0);
Q : out STD_LOGIC
);
end entity;

architecture behavioral of top is
component mux4 is
port(d0,d1,d2,d3: in STD_LOGIC;
x : in STD_LOGIC_VECTOR(1 downto 0);
y : out STD_LOGIC);
end component;

signal y: STD_LOGIC;

begin

mux4x1: mux4 port map ( d0 => d0,
d1 => d1,
d2 => d2,
d3 => d3,
x => x,
y => y );
-- D flip flop process - Sequential Block
top_seq: process(clk)
begin
if(rst) then
Q <= '0';
elsif rising_edge(clk) then
Q <= y;
end if;
end process;

end behavioral;

-- Testbench for TOP level block

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity top_tb is
end;

architecture testbench of top_tb is

component top
port(rst,clk,d0,d1,d2,d3: in STD_LOGIC;
x : in STD_LOGIC_VECTOR(1 downto 0);
Q : out STD_LOGIC
);
end component;

signal rst,clk,d0,d1,d2,d3: STD_LOGIC;
signal x: STD_LOGIC_VECTOR(1 downto 0);
signal Q: STD_LOGIC ;

constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;

begin

uut: top port map ( rst => rst,
clk => clk,
d0 => d0,
d1 => d1,
d2 => d2,
d3 => d3,
x => x,
Q => Q );

stimulus: process
begin
rst <= '1';
d0 <= '0';
d1 <= '1';
d2 <= '0';
d3 <= '1';
x <= "00"; wait for 10 ns;
rst <= '0'; wait for 10 ns;
x <= "00"; wait for 10 ns;
x <= "01"; wait for 10 ns;
x <= "10"; wait for 10 ns;
x <= "11"; wait for 10 ns;

stop_the_clock <= true;
wait;
end process;

clocking: process
begin
while not stop_the_clock loop
clk <= '0', '1' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;

end;

--Simulation Waveform

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