Question

3. Study the VHDL code below for the multiplexer: -mux.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use jeee.std logic.arith.all; entity mux is port DIFF1, DIFF2: n std_logic_vector(4 downto O); ABSLT: out std_logic_vector(4 downto 0); CO: in std logic ); end mux; architecture behv of mux is begin with CO select ABSLT DIFF1 when o, a CO-0 selects B-A DIFF2 when 1',a Co-1 selects A-B "ZZZZZ" when others·.. high impedance otherwise end behy

Answer 1

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all

use ieee.std_logic_arith.all;

entity mux2 is port (

   DIFF1, DIFF2 : in std_logic_vector (4 dowto 0);

   ASLT : out std_logic_vector (4 downto 0);

   CO : in std_logic

);

architecture behv of mux is

begin

with CO select ABSLT <=

DIFF1 when '0',    -- B-A

DIFF2 when '1',    -- A-B

"zzzz" when others; -- High Impedance

end behv;

The above code explains about a mux which has input DIFF1(B-A) and DIFF2(A-B) and the output ABSLT of 5 bits each. It has the select line CO(Carry Out). When CO bit is '0' then the output shows the DIFF1 at the output port. And, when CO bit is '1' then the output shows the DIFF2 at the output port. When the CO is neither '0' or '1' then the output will be High Impedance "ZZZZ".