Question

Name: ·5. (10 lts) Find and correct errors in the following VHDL ed. IEEE ; library use IEEE . STD LOGIC-1104 . all; entity cicuitl is port (a, b, elk: in STD_LOGIC: This part of the code its correct.That is, the entity definition and the 1ibraries are written correctly S out STD LOGIC) ond; architecture synth of eicuiti is begin This part of the code ธhould be a process that groups input a and input b together to forn a 2-bit variable, and then when the signal p: STD _LOGIC_VECTOR (1 downto 0): begin variable is 10a s should output 1, and when the variable's two bita are equal, s should output a, and in all other cases,s should output o. P:= a & b; if p10 then1 elsif p11" then p(0) else s 0' end if: end This part of the code should be a process that groups input a and input b together to form a 2-bit variable, and it should process (clk) variable p: STD LOGIC_VECTOR (1 downto 0) begin if rising edge (clk) then ayi petorm the tollowing logic. q<= y; end ifi (a,b); := p case p is and the process should have a synchronous logic that has two back-to-backD flip-flops, with y being the input, and q being the output. when "01"-> y <= '0'; when "10" "> y <= '11; when others-y'1' end case end process: end;

Answer 1

Flnd and Conect end ' architecture Synth ob Gat S7 be end if end bo irn end it

Cose p is enal caxe end pscce end -There else thos place f- a e have ns the tctal End