Question

in vhdl

Manchester code is a coding scheme used to represent a bit in a data stream. A 'O' value of a bit is represented as a 0-to-1 transition in which the lead half is 'O' and the remaining half is '1'. Similarly, a '1' value of a bit is represented as a 1-to-transition, in which the lead half is 'l' and the remaining half is 0 For example, for the input string "110", the output is translated as: 110 1 1 0 Objectives • Develop State diagram of a Manchester encoder. • Implement with output buffer and lookahead. The entity of the design is defined as: entity ManchesterEncoder is port str_input:in std_logic_vector (7 downto 0); clk: in std_logic; reset: in std logic; str_output: out std_logic end ManchesterEncoder; Deliverables: 1) Report that includes the a. FSM b. ASM CVHDL codes d. Testbench e. Waveforms gathered from the testbench

Answer 1

ASM AND FSM OF MANCHESTER CODING


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o/1 lendo step - o Zero clo P2 level-1 step=1 I level =0 Step- o YP3 ASM one level = 1 Minimized stat Diag, step =0 4 Simpsy oyu can say this Another way to wok There are 2 for manchester code states Sl Transition from 1 to o S2- Transition from 0 to 1 Xo INPOT As in Manchester code it all = 1 Then there is transition from too otherwise of input =0 then there is transition from INPUT Kual ASM
VHDL CODE for MAnchester Coding
library ieee; 
use ieee.std_logic_1164.all; 
entity manchester is
    port (
        clk        : in std_logic;
        resetn     : in std_logic;
        reset      : in std_logic;
        std_output : out std_logic
    );
end manchester;


TESTBENCH

library ieee;
use ieee.std_logic_1164.all;

entity tb_manchester is
end tb_manchester;

architecture tb of tb_manchester is

    component manchester
        port (clk        : in std_logic;
              resetn     : in std_logic;
              reset      : in std_logic;
              std_output : out std_logic);
    end component;

    signal clk        : std_logic;
    signal resetn     : std_logic;
    signal reset      : std_logic;
    signal std_output : std_logic;

    constant TbPeriod : time := 1000 ns; -- EDIT Put right period here
    signal TbClock : std_logic := '0';
    signal TbSimEnded : std_logic := '0';

begin

    dut : manchester
    port map (clk        => clk,
              resetn     => resetn,
              reset      => reset,
              std_output => std_output);

    -- Clock generation
    TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';

    -- EDIT: Check that clk is really your main clock signal
    clk <= TbClock;

    stimuli : process
    begin
        -- EDIT Adapt initialization as needed
        reset <= '0';

        -- Reset generation
        -- EDIT: Check that resetn is really your reset signal
        resetn <= '1';
        wait for 100 ns;
        resetn <= '0';
        wait for 100 ns;

        -- EDIT Add stimuli here
        wait for 100 * TbPeriod;

        -- Stop the clock and hence terminate the simulation
        TbSimEnded <= '1';
        wait;
    end process;

end tb;

-- Configuration block below is required by some simulators. Usually no need to edit.

configuration cfg_tb_manchester of tb_manchester is
    for tb
    end for;
end cfg_tb_manchester;

architecture behaviour of manchester is
    signal p, q, p_next, q_next := '0';
begin
    -- Present state determines the mealy output (q, p) & input (reset)
    q1: process(p, q, reset)
    begin
        std_output <= not reset and p xor q or reset and not p and not q;
        p_next <= not p and reset;
        q_next <= not q and (not p and not reset or reset and q);
    end process;

    -- Clock rising edge during state transition
    q2: process(clk, resetn)
    begin
        if resetn = '0' then
            q <= '0';
            p <= '0';
        elsif clk'event and clk = '1' then
            q <= q_next;
            p <= p_next;
        end IF;
    end process;
end behaviour;