I'm having a hard time writing code for vhdl. Trying to get a 4 bit multipiler...
I'm having a hard time writing code for vhdl. Trying to get a 4 bit multipiler with full adder, however I keep getting errors. Was wondering if you can help me with my code. The question is to design a 4-bit multiplier in VHDL by using component statements.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--entity declaration
entity multi is
port(
A: in std_logic_vector (3 downto 0);
B: in std_logic_vector (3 downto 0);
P: out std_logic_vector (7 downto 0)
);
end entity multi;
--architecture declaration
architecture multiple_4bit of multi is
signal AB0, AB1, AB2,AB3: std_logic_vector (3 downto 0);
--B Inputs (B0 has three bits of AND product)
signal add1,add2, add3: std_logic_vector (3 downto 0);
signal cout0: std_logic_vector (3 downto 0);
signal cout1: std_logic_vector (3 downto 0);
signal cout2: std_logic_vector (2 downto 0);
signal cout3: std_logic_vector (2 downto 0);
--component declaration
component AND_gate is
port( X: in std_logic;
Y: in std_logic;
F: out std_logic
);
end component;
--component declaration
component full_adder
port(
A:in std_logic;
B:in std_logic;
cin:in std_logic;
sum: out std_logic;
cout1: out std_logic;
cout2: out std_logic;
cout3: out std_logic
);
end component;
signal temp: std_logic_vector (3 downto 0);
begin
U0: AND_gate port map (A(0), B(0),AB0(0));
U1: AND_gate port map (A(1), B(0),AB0(1));
U2: AND_gate port map (A(2), B(0),AB0(2));
U3: AND_gate port map (A(3), B(0),AB0(3));
U4: AND_gate port map (A(4), B(0),AB0(4));
U5: AND_gate port map (A(0), B(1),AB0(0));
U6: AND_gate port map (A(1), B(1),AB0(1));
U7: AND_gate port map (A(2), B(1),AB0(2));
U8: AND_gate port map (A(3), B(1),AB0(3));
U9: AND_gate port map (A(0), B(2),AB0(0));
U10:AND_gate port map (A(1), B(2),AB0(1));
U11:AND_gate port map (A(2), B(2),AB0(2));
U12:AND_gate port map (A(3), B(2),AB0(3));
U13:AND_gate port map (A(0), B(3),AB0(0));
U14:AND_gate port map (A(1), B(3),AB0(1));
U15:AND_gate port map (A(2), B(3),AB0(2));
U16:AND_gate port map (A(3), B(3),AB0(3));
U17: full_adder port map (cin, AB0(1), AB1(0), add1(0),
cout1(0));
U18: full_adder port map (cout1(0), AB0(2), AB1(1), add1(1),
cout1(1));
U19: full_adder port map (cout1(1), AB0(3), AB1(2), add1(2),
cout1(2));
U20: full_adder port map (cout1(2), cin, AB1(3), add1(3),
cout1(3));
U21: full_adder port map (cin, AB2(0), add1(1), add2(0),
cout2(0));
U22: full_adder port map (cout2(0), AB2(1), add1(2), add2(1),
cout2(1));
U23: full_adder port map (cout2(1), AB2(2), add1(3), add2(2),
cout2(2));
U24: full_adder port map (cout2(2), AB2(3), cout1(3), add2(3),
cout2(3));
U25: full_adder port map (cin, AB3(0), add2(1), add3(0),
cout3(0));
U26: full_adder port map (cout3(0), AB3(1), add2(2), add3(1),
cout3(1));
U27: full_adder port map (cout3(1), AB3(2), add2(3), add3(2),
cout3(2));
U28: full_adder port map (cout3(2), AB3(3), cout2(3), add3(3),
cout3(3));
-- output definitions P
p(0) <= AB0(0);
p(1) <= add1(0);
p(2) <= add2(0);
p(3) <= add3(0);
p(4) <= add3(1);
p(5) <= add3(2);
p(6) <= add3(3);
p(7) <= cout3(3);
end multiple_4bit;
Homework Answers
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--entity declaration
entity multi is
port(
A: in std_logic_vector (3 downto 0);
B: in std_logic_vector (3 downto 0);
P: out std_logic_vector (7 downto 0)
);
end entity multi;
--architecture declaration
architecture multiple_4bit of multi is
signal AB0, AB1, AB2,AB3: std_logic_vector (3 downto 0);
--B Inputs (B0 has three bits of AND product)
signal add1,add2, add3: std_logic_vector (3 downto 0);
signal cout0: std_logic_vector (3 downto 0);
signal cout1: std_logic_vector (3 downto 0);
signal cout2: std_logic_vector (2 downto 0);
signal cout3: std_logic_vector (2 downto 0);
--component declaration
component AND_gate is
port( X: in std_logic;
Y: in std_logic;
F: out std_logic
);
end component;
--component declaration
component full_adder
port(
A:in std_logic;
B:in std_logic;
cin:in std_logic;
sum: out std_logic;
cout1: out std_logic;
cout2: out std_logic;
cout3: out std_logic
);
end component;
signal temp: std_logic_vector (3 downto 0);
begin
cin <= '0';U0: AND_gate port map (A(0), B(0),AB0(0));
U1: AND_gate port map (A(1), B(0),AB0(1));
U2: AND_gate port map (A(2), B(0),AB0(2));
U3: AND_gate port map (A(3), B(0),AB0(3));
U5:AND_gate port map (A(0), B(1),AB1(0));
U6: AND_gate port map (A(1), B(1),AB1(1));
U7: AND_gate port map (A(2), B(1),AB1(2));
U8: AND_gate port map (A(3), B(1),AB1(3));
U9: AND_gate port map (A(0), B(2),AB2(0));
U10:AND_gate port map (A(1), B(2),AB2(1));
U11:AND_gate port map (A(2), B(2),AB2(2));
U12:AND_gate port map (A(3), B(2),AB2(3));
U13:AND_gate port map (A(0), B(3),AB3(0));
U14:AND_gate port map (A(1), B(3),AB3(1));
U15:AND_gate port map (A(2), B(3),AB3(2));
U16:AND_gate port map (A(3), B(3),AB3(3));
U17: full_adder port map (cin, AB0(1), AB1(0), add1(0),
cout1(0));
U18: full_adder port map (cout1(0), AB0(2), AB1(1), add1(1),
cout1(1));
U19: full_adder port map (cout1(1), AB0(3), AB1(2), add1(2),
cout1(2));
U20: full_adder port map (cout1(2), cin, AB1(3), add1(3),
cout1(3));
U21: full_adder port map (cin, AB2(0), add1(1), add2(0),
cout2(0));
U22: full_adder port map (cout2(0), AB2(1), add1(2), add2(1),
cout2(1));
U23: full_adder port map (cout2(1), AB2(2), add1(3), add2(2),
cout2(2));
U24: full_adder port map (cout2(2), AB2(3), cout1(3), add2(3),
cout2(3));
U25: full_adder port map (cin, AB3(0), add2(1), add3(0),
cout3(0));
U26: full_adder port map (cout3(0), AB3(1), add2(2), add3(1),
cout3(1));
U27: full_adder port map (cout3(1), AB3(2), add2(3), add3(2),
cout3(2));
U28: full_adder port map (cout3(2), AB3(3), cout2(3), add3(3),
cout3(3));
-- output definitions P
p(0) <= AB0(0);
p(1) <= add1(0);
p(2) <= add2(0);
p(3) <= add3(0);
p(4) <= add3(1);
p(5) <= add3(2);
p(6) <= add3(3);
p(7) <= cout3(3);
end multiple_4bit;
Add Answer to:
I'm having a hard time writing code for vhdl. Trying to get a 4
bit multipiler...
QUESTION 1 Complete the following peice of VHDL code with the necessary VHDL statements for a...
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Draw the RTL schematic of the hardware that will be synthesized for the VHDL code below....
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Write a VHDL code using processes for the following logic circuit which include a shift register...
Write a VHDL code using processes for the following logic
circuit which include a shift register and 4x1 multiplexer. Use the
entity below.
entity registers_min_max is
port( din : in std_logic_vector(3 downto 0);
reset : in std_logic;
clk : in
std_logic;
sel : in
std_logic_vector(1 downto 0);
reg_out : out std_logic_vector(3
downto 0));
end registers_min_max;
din reset RO clk reset R1 A C clk reset R2 clk reset R3 clk 3 0 sel LE
b. Suppose you are provided with a 4-bit ripple carry adder. It has the following entity...
b. Suppose you are provided with a 4-bit ripple carry adder. It has the following entity declaration and schematic representation А(3:0] B[3: entity fourbit FA is portA, B in std logic_vector (3 downto 0); 4-bit RCA Cin in std_logic; S out stdlogic_vector (3 downto 0) Cout out std logic: Cin Cout S3:0] end fourbitFA Create a VHDL architecture for the following circuit (15 Marks) C3:0] D[3:0] A[3:0] B[3:0] Е[3:0] F[3:0] 4-bit RCA 4-bit RCA inA 4-bit RCA CinB CinC Coutl...
8.(5 points).There is an error in following VHDL code. Find the error and correct (only that...
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in vhdl Manchester code is a coding scheme used to represent a bit in a data...
in vhdl
Manchester code is a coding scheme used to represent a bit in a data stream. A 'O' value of a bit is represented as a 0-to-1 transition in which the lead half is 'O' and the remaining half is '1'. Similarly, a '1' value of a bit is represented as a 1-to-transition, in which the lead half is 'l' and the remaining half is 0 For example, for the input string "110", the output is translated as: 110...
Write a test bench for the following VHDL code -------------------------------------------------------------------------------------------------------------------------------- LIBRARY ieee ; USE ieee.std_logic_1164.all ;...
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Write a VHDL code using processes for the following logic
circuit which include a shift register and 4x1 multiplexer. Use the
entity below.
entity registers_min_max is
port( din : in std_logic_vector(3 downto 0);
reset : in std_logic;
clk : in
std_logic;
sel : in
std_logic_vector(1 downto 0);
reg_out : out std_logic_vector(3
downto 0));
end registers_min_max;
din reset RO clk reset R1 A C clk reset R2 clk reset R3 clk 3 0 sel LE
b. Suppose you are provided with a 4-bit ripple carry adder. It has the following entity declaration and schematic representation А(3:0] B[3: entity fourbit FA is portA, B in std logic_vector (3 downto 0); 4-bit RCA Cin in std_logic; S out stdlogic_vector (3 downto 0) Cout out std logic: Cin Cout S3:0] end fourbitFA Create a VHDL architecture for the following circuit (15 Marks) C3:0] D[3:0] A[3:0] B[3:0] Е[3:0] F[3:0] 4-bit RCA 4-bit RCA inA 4-bit RCA CinB CinC Coutl...
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in vhdl
Manchester code is a coding scheme used to represent a bit in a data stream. A 'O' value of a bit is represented as a 0-to-1 transition in which the lead half is 'O' and the remaining half is '1'. Similarly, a '1' value of a bit is represented as a 1-to-transition, in which the lead half is 'l' and the remaining half is 0 For example, for the input string "110", the output is translated as: 110...
3. Study the VHDL code below for the multiplexer: -mux.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use jeee.std logic.arith.all; entity mux is port DIFF1, DIFF2: n std_logic_vector(4 downto O); ABSLT: out std_logic_vector(4 downto 0); CO: in std logic ); end mux; architecture behv of mux is begin with CO select ABSLT DIFF1 when o, a CO-0 selects B-A DIFF2 when 1',a Co-1 selects A-B "ZZZZZ" when others·.. high impedance otherwise end behy
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