Question

Write the source code for a 16-bit adder using the ‘+’ operator. Use the following information as a guide:

a. Use the names in the Adder Symbol/diagram above to name your block and its ports (all lower-case). For example dataa[15:0] signal name in VHDL would be dataa : in unsiged (15 downto 0);
b. All inputs and outputs should be declared as type UNSIGNED vs STD_LOGIC_VECTOR. c. Do not worry about rollover with this adder. This adder is already wide enough to account for all the values it will be adding together.

d. Make sure to include the library and package declarations at the beginning of the file. You will need the IEEE.NUMERIC_STD package. e. If you would prefer using a different text editor, please feel free to do so. Just make sure you save your VHDL file in the project directory.

bleow is the code

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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY adder_tb IS
END ENTITY adder_tb;

ARCHITECTURE stimulus OF adder_tb IS

   -- Component declaration for adder block
   COMPONENT adder
       PORT(
           dataa, datab: IN UNSIGNED(15 DOWNTO 0);
           sum: OUT UNSIGNED(15 DOWNTO 0)
       );
   END COMPONENT;

   -- Signals to connect to DUT
   SIGNAL dataa, datab, sum : UNSIGNED (15 DOWNTO 0);

BEGIN -- beginning of architecture body

   -- instantiate unit under test (adder)
   adder1 : adder PORT MAP
       (dataa => dataa, datab => datab, sum => sum);

   -- Assign values to "dataa" and "datab" to test adder block
   dataa <= x"0008", x"0000" AFTER 20 NS, x"000A" AFTER 30 NS;
   datab <= x"0005", x"0001" AFTER 20 NS, x"0005" AFTER 30 NS;
      
END ARCHITECTURE stimulus;

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity adder is
   PORT(
dataa, datab: IN UNSIGNED(15 DOWNTO 0);
sum: OUT UNSIGNED(15 DOWNTO 0)
);
end adder;

architecture arch of adder is

begin

   sum <= dataa + datab;

end arch;

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--Simulation on ModelSim