Question

VHDL QUESTION:

How can i make a FULL ADDER instantiating a HALF ADDER}

THIS IS MY HA CODE:

library IEEE;
use IEEE.std_logic_1164.ALL;

entity HA is
   port(A, B: in bit;
           SUM, CARRY: out bit);
end HA;

architecture RTL of HA is
begin
       SUM <= A xor B;
       CARRY <= A and B;

       end RTL;

CAN SOMEONE EXPLAIN ME HOW IT WORKS TO INSTANCIATE COMPONENTS IN VHDL AND HOW TO MAKE THE FA WITH THIS ?

Answer 1

Logic diagram for full adder using two half adders:

The full adder requires 3 components- two half adders(h1 and h2)  and an OR gate(r1)

For the half adder r1 ,the inputs are A,B and the outputs are S1,C1

For the half adder r2 ,the inputs are s1,Cin and the outputs are S, c2

For OR gate r1, the inputs are c1 ,c2 and the output is C

VHDL code:

HA.vhdl
________
entity HA is
port(A, B: in bit;
SUM, CARRY: out bit);
end HA;

architecture RTL of HA is
begin
SUM <= A xor B;
CARRY <= A and B;

end RTL;
____________________________________________________
or1.vhdl
_________
entity or1 IS
PORT(A,B: in bit;
C :out bit);
END or1;
ARCHITECTURE dataflow of or1 IS
BEGIN
C <= A or B;
END dataflow;
________________________________________________________
fa.vhdl
_________
entity fulladder is
port(A,B,Cin: in bit;
S, C : out bit);
end fulladder;

architecture structural of fulladder is
component HA
port(A,B,Cin:in bit;
S,C;out bit);
end component;

component or1
port(A,B: in bit;
C : out bit);
end Component;

signal s1,c1,c2:std_logic;
begin
h1: HA port map(A,B,s1,c1);
h2: HA port map(s1,Cin,S,c2);
r1: or1 port map(c1,c2,C);
end structural;
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