Please fully answer BOTH parts of the question (a) and (b). a) Draw the high level...
Please fully answer BOTH parts of the question (a) and (b).
a) Draw the high level synthesized diagram of the following VHDL code. What does the following circuit do? Write the sequence of output generated by this circuit.
library ieee;
use ieee.std_logic_1164.all;
entity sequence is
port (
cout :out std_logic_vector (3 downto 0);
clk :in std_logic;
reset :in std_logic
);
end entity;
architecture rtl of sequence is
signal count :std_logic_vector (3 downto 0);
begin
process (clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
count <= "0001";
else
count <= (count(2) & count(1) & count(0) & count(3));
end if;
end if;
end process;
cout <= count;
end architecture;
b)How does the function of this circuit change if the statement inside the process changes to the following? What would be the change in the block diagram you drew in the first part? Write the sequence of output generated by this circuit.
count <= (count(2) & count(1) & count(0) & not count(3));
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Please fully answer BOTH parts of the question (a) and (b).
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