Question

PROBLEM 3 (16 PTS) ▪ With a D flip flop and logic gates, sketch the circuit whose excitation equation is given by:

PROBLEM 3 (16 PTS) • With a D flip flop and logic gates, sketch the circuit whose excitation equation is given by: Qit+1) + y + Q(t) + y(t) (4 pts) • Complete the timing diagram of the circuit whose VHDL description is shown below. Also, get the excitation equation for q. library ieee: elsaf (cll'event and clk = '1') then use ieee.std_logic_1164.all: if x = '1' then a or not (t): entity circ is end it. port (cirn, elk, a: in std_logic; end at: go out std Logic; end process: end eine g ot: end t: architecture t of circ is cinthhhhhhhhh signal qt: std_logic; begin process (clrn, clk 2, al begin if clon = 'O' then q(t+1) = . Given the following circuit, get the excitation equations for each flip flop output Q = 0.0.0.Q. (6 pts) AQ reset HLADA

Answer 1

W, 0(+) € ãy + Q (+) +y @ (t) | * Q(++) is next output of flipflop and Q (t? is present scade cutput ogleplylop. Here there are two extanal Enputs & andy. * By Characteristic equation of Dobelspillop I olttilo next output is equal to D-flipflop input. so To = Q(+1) = 5x + 2 Q (+9+90(+) circuit diagram 1 (+) 1 Clock COCK e Derepectq the excitation equation of 19 (t+1) =( Q xroy 914) previous output Present output

for Given VHOC deserfation rining diogram --- ப ட - - | - - - - - - - - - - - - , 1 'As t> Asx=6 c(arap so, Az0| aurg | ('

Excitation equations for each outputs are r ** = (@z Gol @ s Flip flop s son at Po Next output q psiesent Output 0 = a, © (A2.03) | @= @ @ GsQ3) + Neat outputs depends on present outputs and inputs.