1.Please use 5-stage pipeline to describe following MIPS assembly code in non-forwarding pipeline.
lw $s0, 0($t0)
add $s1, $s0, $s0
mul $s2, $s1, $s0
. 2.Please use 5-stage pipeline to describe following MIPS assembly code in forwarding pipeline.
lw $s0, 0($t0)
add $s1, $s0, $s0
mul $s2, $s1, $s0
sw $s2, 4($t0)
1.
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | |
| Inst 1 | IF | ID | EX | MEM | WB | ||||||
| Inst 2 | IF | ID | STALL | STALL | EX | MEM | WB | ||||
| inst 3 | IF | STALL | STALL | ID | STALL | STALL | EX | MEM | WB |
2.
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | |
| Inst 1 | IF | ID | EX | MEM | WB | |||
| Inst 2 | IF | ID | EX | MEM | WB | |||
| Inst 3 | IF | ID | EX | MEM | WB | |||
| Inst 4 | IF | ID | EX | MEM | WB |
1.Please use 5-stage pipeline to describe following MIPS assembly code in non-forwarding pipeline. lw $s0, 0($t0)...
7 [24 marks] Consider the following MIPS code segment that is executed on a 5-stage pipeline architecture that does not implement forwarding or stalling in hardware. (1) add $4, $1, $1 (2) add $7, $4, $9 (3) lw $2, 40($8) (4) sub $8, $1, $2 (5) sw $8, 80(S2) (6) sub $2, $8, $4 (7) lw S8, 2($1) (8) add $8, $4, S2 Identify the data dependences that cause hazards. You are to use the following format to inform each...
The following MIPS assembly code contains a mistake that violates the MIPS convention in terms of using stack for storing/protecting registers. What is the mistake and how should it be fixed? Correct the corresponding lines in the code. For the corrected code, sketch the stack frame contents at the time when the instruction ‘move $s1, $a1’ is being executed. f: addi $sp, $sp, 12 sw $ra, 8($sp) sw $s1, 4($sp) sw $s0, 0($sp) move $s0, $a0 move $s1, $a1 #...
1. Given the following instruction sequence for the MIPS processor with the standard 5 stage pipeline $10, S0. 4 addi lw S2.0(S10) add sw S2,4(510) $2, $2, $2 Show the data dependences between the instructions above by drawing arrows between dependent instructions (only show true/data dependencies). a. Assuming forwarding support, in what cycle would the store instruction write back to memory? Show the cycle by cycle execution of the instructions as they execute in the pipeline. Also, show any stalls...
Consider the following MIPS code segment that is executed on a 5-stage pipeline architecture that does not implement forwarding or stalling in hardware. (1) add $4, $1, $1 (2) add $7, $4, $9 (3) lw $2, 40($8) (4) sub $8, $1, $2 (5) sw $8, 80($2) (6) sub $2, $8, $4 (7) lw $8, 2($1) (8) add $8, $4, $2 Identify the data dependences that cause hazards. You are to use the...
What are the machine codes for the following MIPS assembly codes? a. sub $t0, $s0, $s1 b. lw $t0, 20($s0)
The Following source code has a stalling problem: lw $st3, 4($t0) lw $st4, 8($t0) sub $s1, $st3, $st4 sw $s1, 12($t0) lw $t5,16($t0) add $s2, $t3,$t5 sw $s2,20($t0) Rearrange the code sequence that does exactly the same job without stalling:
2.4 For the MIPS assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. sll $t0, $s0, 2 # $t0 = f * 4 add $t0, $s6, $t0 # $t0 = &A[f] sll $t1, $s1, 2 # $t1 =...
The following MIPS program is to be run on a MIPS pipeline processor of 5 stages (IF-ID-EX-MEM-WB). Work out and diagram the optimal pipeline schedule using full forwarding from EX or MEM stages to any other stage, Draw the pipeline execution diagram for this code and then compute the pipeline CPI: addi $t6, $t6, 10 sub $t5, $t6, $t4 srl $t5, $t5, 2 sw $t5, 20($t5) lw $t2, 0($t6) add $t7, $t2, $t3 beq $t5, $t7, End
Computer organization
6) Given the MIPS five stage pipeline and the following instruction sets: [30 pts, 10 pts each] instruction set #1 1w $1, 40 ($6) add $2, $3, $1 add $1, $6, $4 and $1, $1, $4 sw $2, 20 ($4) instruction set #2 add $1, $5, $3 sw$1, 0 ($2) lw $1, 4 ($2) add $5, $5, $1 sw$1, 8 ($2) a) If there is no forwarding or hazard detection, write the instructions (same order) and insert nop's...
Given the following sequence of instructions: lw $s2, 0($s1) //1 lw $s1, 40($s3) //2 sub $s3, $s1, $s2 //3 add $s3, $s2, $s2 //4 or $s4, $s3, $zero //5 sw $s3, 50($s1) //6 a. List the read after write (current instruction is reading certain registers which haven’t been written back yet) data dependencies. As an example , 3 on 1 ($s2) shows instruction 3 has data dependency on instruction 1 since it is reading register $s2. b. Assume the 5...