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b) Compute the miss penalty to transfer 8 words cache block from DRAM, where it takes...

b) Compute the miss penalty to transfer 8 words cache block from DRAM, where it takes 2
memory bus cycles to send the address, 25 memory bus cycles for DRAM access time and 3
memory bus cycles to send one word of data for the following three organizations: (i) Oneword-wide memory organization, (ii) Wide memory organization (4-word wide) and (iii)
Interleaved memory organization (4 banks). Show all your work to get full credit.

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