Question

Q4. CISC/RISC and Cache Memory (24pts)

Q4-1. Assume that UltraSpark-like processor has an L1 cache with the following specifications:

• 40-bit wide address and 64-bit wide data busses
• On-chip instruction cache
• Cache is 16K bytes, organized as a 2-way set associative
• Cache line (block) size = 64 bytes
• 200 MHz clock frequency
• Average cache hit rate = 90%
• Instructions located in cache execute in 1 clock cycle

Instructions that are not found in the on-chip cache will cause the processor to stop all program execution and do a burst memory read access of one refill line from main memory to the cache.

For this memory design, burst accesses from main memory requires an address set-up time of 64 clock cycles, and then all subsequent burst fetches from main memory require 8 clock cycles per memory fetch.

Q4-1-i. Calculate 1 clock cycle, (i.e., the time length of 1 clock) (3pts)

Your answer:

Q4-1-ii. How many memory fetches must be done upon a cache miss? (3pts)

Your answer:

Q4-1-iii. Calculate CPU cycles required to read data from system memory upon a cache miss. (# clocks but not time) (3pts)

Your answer:

Q4-1-iv. What is the effective instruction execution time for this UltraSpark-like processor? (3pts)

Your answer:

Answer 1

Data bus size = 64 bit = 8 bytes
Block size = 64 bytes
Number of access needed to fetch 1 Block = 64/8 = 8

clock frequency = 200 MHz

(i)1 clock cycle = 1/(200 * 106) = 5 * 10-9 = 5 nanosecond

(ii)Number of memory fetches = 8
(iii)Total number of cycle needed = 64 + 8*8 = 128 cycles.
(iv) The effective instruction execution time
=> (0.9 * 1) + (0.1 * 128) = 13.7 cycles
=> 13.7 * 5 nanoseconds = 68.5 nanoseconds