Question

Designing reliable CMOS chips involves understanding and addressing potential failure modes of the technology. Elaborate on three reliability problems, commonly known as hard errors, that cause integrated circuits (ICs) to fail permanently particularly when the ICs are operating at high temperatures ( > 100 °C) for high speed circuit applications in sub-micron node technologies

Answer 1

The following are the three reliability problems that can cause Integrated circuits to fail permanently while they are operating at high temperature.

They are,

1. Time-Dependent Dielectric Breakdown
2. Hot Carriers
3. Negative Bias Temperature Instability

Let us briefly discuss each problems and its effect.

1. Time-Dependent Dielectric Breakdown:

Dielectric breakdown is defined as the failure of a dielectric substance to withstand the applied electrical stress due to the electric field. This breakdown occurs when the electrical field becomes extremely sufficient enough to cause some amount of a dielectric to switch from being an electrical insulator to a partial conductor. Dielectric breakdown can result between interface of two dielectrics or inside a single dielectric. It may occur as a series of small discharges over time that will progressively damage (time dependent) the dielectric to the point where it eventually fails catastrophically.

When the electric field is applied across the gate oxide of CMOS Integrated circuit, the gate current (I_c) increases gradually which is called to be time-dependent dielectric breakdown (TDDB). The elevated gate current due to the applied electric field is called as stress-induced leakage current (SILC). Time dependent dielectric breakdown likely results from a combination of charge injection, trap-assisted conduction and generation of trap state . After sufficient
stress, it can result in catastrophic dielectric breakdown that short-circuits the gate.

2. Hot Carriers:

The aging mechanism in addition to variations translate into complexity and reduced design margin for circuits. Aging due to
Hot carrier injection is the important cause of functional failure in large scale circuits. These issues will result in "Design for Reliability". A failure is a deviation from compliance with the system specification for a given period
of time.

While the transistors switch, high-energy carriers named as "hot carriers" are injected occasionally
into the gate oxide region and become trapped. Electrons have higher mobility and these electrons will result in the generation of most of the hot carriers. The damaged oxide changes the Voltage-Current characteristics of the cirucit. This will result in current increase in pMOS transistors and reduction of current in nMOS transistors. When the substrate current (I_sub) is relatively large, damage to the device is maximized. This will happen when nMOS transistors see a large drain-source voltage V_ds while the transistor is ON. Hence the problem is worst for inverters and NOR gates with fast rising inputs and heavily loaded outputs, and for high power supply voltages. Hot carriers may result in circuit wear out as nMOS transistors become too slow.

3. Negative Bias Temperature Instability(NBTI):

Negative bias instability due to temperature increase the threshold voltage and consequent decrease in drain current(Id). Decrease in drain current reduces the trans-conductance of a circuit. This degradation is often approximated by a power-law dependence on time.

It is a shift in threshold voltage with applied stress. When an electric field is applied across a gate oxide, dangling bonds called "traps" develop at the Si-SiO₂ interface. The threshold voltage increases as more traps form, reducing the drive current until the circuit fails. When the applied shift exceeds a specific value, the device is considered to be failed. In smaller devices, the time to failure due to negative bias instability varies widely such as devices fail very quickly.When the stress is removed, few devices recover quickly in few seconds, while others fail to recover over the longest intervals.. While failure and recovery are both bias-dependent, the time constants of the two phenomena are not the same.

The process is most pronounced for pMOS transistors with a strong negative bias because of V_gs = 0 V and V_s= V_dd at high temperature.