Question

Suppose that mispredictions need a 4 cycle stall and the branch prediction algorithm has an accuracy of 95%. Empirical evidence indicates that 1/7 of all instructions are branches. Also assume that you are running the MIPS pipelined architecture at 2GHz, except that all data hazards are handled by forwarding.

What is the throughput of the resulting processor?

Answer 1

%age of branch instruction = 1/7 * 100 = 14.28% or 0.1428

%age of non-branch instruction = 100-14.28% = 85.72 or 0.8572

%age of branch instructions that can be handled by branch predictor correctly = 95% or 0.95

%age of branch instructions that cannot be handled by branch predictor correctly = 100 - 95% = 5% or 0.05

Clock rate = 2GHz.

CPI for non-branch instructions = 1

CPI for branch instructions = 4 + 1 = 5

Average CPI = fraction of non-branch instruction * CPI for non-branch instruction + fraction of branch instruction * CPI for branch instruction

Average CPI = 0.8572 * 1 + 0.1428 * 5 = 1.5712

=> average CPI = 1.5712

=> Throughput:

MIPS rate = Clock rate/(Average CPI * 10⁶ ) = 2 x 10⁹ / (1.5712 * 10⁶ ) = 1.27291242 x 10³ = 127

=> Throughput is approx. 127 Million instructions per second