QUESTION 10 The purpose of virtual memory is to use ……… to increase the available address...
QUESTION 10
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The purpose of virtual memory is to use ……… to increase the available address space a process can use.
A. hard disk as an extension of RAM
B. RAM as an extension of CPU
C. registers as an extension of arithmetic logic unit (ALU)
D. cache as an extension of registers
Homework Answers
Hard disk as an extension of RAM
When a computer uses its total RAM then the pages which are not in use are transferred to hard drive in the virtual memory
So to increase the available address space it uses the virtual memory hard disk as an extension of RAM.
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QUESTION 10
The purpose of virtual memory is to use ……… to increase the
available address...
Question 6 For the following figure shows a hypothetical memory hierarchy going from a virtual address to L2 cache acce...
Question 6 For the following figure shows a hypothetical memory hierarchy going from a virtual address to L2 cache access. The page size is 8KB, the TLB is direct mapped with 128 entries. The L1 cache is a direct mapped 8 KB, and the L2 cache is 2MB and direct mapped. Both use 64 byte blocks. The virtual address is 64 bits and the physical address is 41 bits. For each block in the figure below, fill in the number...
Virtual memory address translation: a) Consider a machine with a physical memory of 8 GB, a...
Virtual memory address translation: a) Consider a machine with a physical memory of 8 GB, a page size of 4 KB, and a page table entry size of 4 bytes. How many levels of page tables would be required to map a 52-bit virtual address space if every page table fits into a single page? b) Without a cache or TLB, how many memory operations are required to read or write a page in physical memory? c) How much physical...
QUESTION 16 In the ARM Cortex MO core which register holds the memory address of the...
QUESTION 16 In the ARM Cortex MO core which register holds the memory address of the next instuction to be loaded from memory and usually increments by 2 when each instruction is executed? O a. Address register b.Instruction register C. Register bank d. Arithmetic and logic unit (ALU) Program counter ■ f. Instruction decoder ■ g. Control unit Z e.
QUESTION 1 Virtual Memory is a technique that makes excellent use of available space on a...
QUESTION 1 Virtual Memory is a technique that makes excellent use of available space on a hard drive, to temporarily store data that would otherwise require massive amounts of main memory (RAM). True False 2 points QUESTION 2 Which of these allocation schemes require the entire program to be loaded before execution can begin? I. Segmented/Demand paged II. Paged III. Segmented IV. Demand paged 2 points QUESTION 3 Select the advantages of the First-In First-Out page replacement policy...
Problem #1 (25 points) Address Space, Memory Consider a hypothetical 18-bit processor called HYP18 with all...
Problem #1 (25 points) Address Space, Memory Consider a hypothetical 18-bit processor called HYP18 with all registers, including PC and SP, being 18 bits long. The smallest addressable unit in memory is an 8-bit byte. A. (4 points) What is the size of HYP18's address space in bytes and KB? How many address lines does HYP18 require? Address space: Bytes Address space: KB (KiloBytes). Address bus lines: B. (6 points) Assume that first quarter of the address space is dedicated...
16 It is known that computer system programs use 32-bit virtual addresses to access storage units....
16 It is known that computer system programs use 32-bit virtual addresses to access storage units. If the physical memory space of the computer system is 1GB, and the paging management mechanism is adopted, the page size is 4KB, and each page table entry is 4B. If only one level of page table is used to realize the mapping from virtual address to physical address, how much memory space does the page table occupy? A. 1MB B. 4KB C. 1KB...
Computer architecture Question 26 What is a required feature in order to implement the virtual memory?...
Computer
architecture
Question 26 What is a required feature in order to implement the virtual memory? (check all that are true) Physical address space larger than virtual address space Assembly instructions to go back and forth between user mode and kernel mode A multicore CPU The use of an Operating System (OS) An ISA that supports at least two privilege levels.
1. (5 points) 1.14 What is the purpose of interrupts? What are the differences between a...
1. (5 points) 1.14 What is the purpose of interrupts? What are the differences between a trap and an interrupt? Can traps be generated intentionally by a user program? If so, for what purpose? 2. (5 points) 1.19 Rank the following storage systems from slowest to fastest: a. Hard-disk drives b. Registers c. Optical disk d. Main memory e. Nonvolatile memory f. Magnetic tapes g. Cache
Assignment 2 1. In real-address mode, convert the following segment offset address to a linear address:...
Assignment 2 1. In real-address mode, convert the following segment offset address to a linear address: 0950:0100 2. In real-address mode, convert the following segment offset address to a linear address: 0CD1:02E0 3. What is the duration of a single clock cycle (in nanoseconds) in a 3.4 GHz 4. A hard disk rotates at 4200 RPM (rotations per minute). What is the timeof one rotation in milliseconds? 5. Which Intel processor was the first member of the IA-32 family? 6....
construction of a physical address, page tables are stored in a special cache calied a A....
construction of a physical address, page tables are stored in a special cache calied a A. Page translation lookup table 8 Translation look aside buffer C. Set associative address cache D. Page table associative block A system that uses virtual addresses contains a special 1P block to construct and manage address A. Memory Management Unit B. Rapid Address Constructor Unit ALU bypass Address Generator D. All the above E. None of the above peripheral devices connected to the ARM are...
Question 6 For the following figure shows a hypothetical memory hierarchy going from a virtual address to L2 cache access. The page size is 8KB, the TLB is direct mapped with 128 entries. The L1 cache is a direct mapped 8 KB, and the L2 cache is 2MB and direct mapped. Both use 64 byte blocks. The virtual address is 64 bits and the physical address is 41 bits. For each block in the figure below, fill in the number...
QUESTION 16 In the ARM Cortex MO core which register holds the memory address of the next instuction to be loaded from memory and usually increments by 2 when each instruction is executed? O a. Address register b.Instruction register C. Register bank d. Arithmetic and logic unit (ALU) Program counter ■ f. Instruction decoder ■ g. Control unit Z e.
Problem #1 (25 points) Address Space, Memory Consider a hypothetical 18-bit processor called HYP18 with all registers, including PC and SP, being 18 bits long. The smallest addressable unit in memory is an 8-bit byte. A. (4 points) What is the size of HYP18's address space in bytes and KB? How many address lines does HYP18 require? Address space: Bytes Address space: KB (KiloBytes). Address bus lines: B. (6 points) Assume that first quarter of the address space is dedicated...
Computer
architecture
Question 26 What is a required feature in order to implement the virtual memory? (check all that are true) Physical address space larger than virtual address space Assembly instructions to go back and forth between user mode and kernel mode A multicore CPU The use of an Operating System (OS) An ISA that supports at least two privilege levels.
1. (5 points) 1.14 What is the purpose of interrupts? What are the differences between a trap and an interrupt? Can traps be generated intentionally by a user program? If so, for what purpose? 2. (5 points) 1.19 Rank the following storage systems from slowest to fastest: a. Hard-disk drives b. Registers c. Optical disk d. Main memory e. Nonvolatile memory f. Magnetic tapes g. Cache
construction of a physical address, page tables are stored in a special cache calied a A. Page translation lookup table 8 Translation look aside buffer C. Set associative address cache D. Page table associative block A system that uses virtual addresses contains a special 1P block to construct and manage address A. Memory Management Unit B. Rapid Address Constructor Unit ALU bypass Address Generator D. All the above E. None of the above peripheral devices connected to the ARM are...
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