Explain what changes would be necessary to add the jr instruction to the single-cycle datapath and control.
Adding JR to the datapath:---

JR instruction sets the PC to the content of the register, so we
have to provide a way for this data from the register file (Read
data 1 port).
Next, a mux is needed to control whether the PC will take the value
coming from the register file via the added wire or not.
Finally, a signal has to be led from the controller to the newly
added mux to control it.
These three hardware modifications are highlighted in yellow on the
diagram above.
Explain what changes would be necessary to add the jr instruction to the single-cycle datapath and...
4. (10 pts) The following MIPS single-cycle datapath cannot perform Divide instruction. Indicate any changes to the datapath that must be done in order to support Div instruction, e.g., adding extra wires, extra logic gates, extra registers, etc. Do your modification on the following figure if necessary, and show the dataflow for this instruction using dash lines on the modified figure. Also show the values of the corresponding control signals in the following table and add new control signals to...
Describe the modifications to the single clock cycle datapath that would be needed to implement the jalr instruction, and give the control signal settings that would be required for this instruction.
Describe the modifications to the single clock cycle datapath that would be needed to implement the jalr instruction (jump and link register), and give the control signal settings that would be required for this instruction.
Pad 1:58 PM * 51% --|- Objectives. Learn how to enhance the datapath and control for both the single cycle and multicycle implementa- tions of a simple ALU Below is table that indicates which control lines are set for each type of instruction for the single- cycle implementation shown in Figure 4.24 of your textbook, which is also shown on the following page. Indi- cate the setting for each control line to support the addiu instruction, which should not require...
6. Consider a datapath similar to the one in figure below, but for a processor that only has one type of instruction: unconditional PC-relative branch. What would the cycle time be for this datapath? PCSrc Add ALU Add result Shift +( left 2 Read register 1 ALUSrc, 4 ALU operation PCRead PC-address Read data 1 Registers Read data 2 MemWrite Zero ALU ALU-I Address MemtoReg Instruction register 2 Instruction | Write Read data-M register Write Lu memory Write Data data...
Question 4: Single Cycle Datapath Control (15 points) We wish to add the hardware support for a special R-type instruction jlr Jump and Link Register) to the single-cycle datapath below. Though this is an R-type instruction, but it is a special one that has the opcode being 000001 (instead of 000000), so the control unit will be able to differentiate this jlr instruction from the other R-type instructions and generate a special set of controls for this instruction. Opcode rs...
*For a clearer view of the datapath*
Answer choices for all
Consider the MIPS single cycle datapath shown below. Select the correct control signals that will be generated by the control unit for the following instruction: andi $t0,$t1,4 Instruction (25-01 Shin Jump address (31-0) - left 2) 28 PC +4 [31-28) XCS result left 2 RegDst Jump Branch MemRead Instruction (31-26] MemtoReg Control ALUOP MemWrite ALUSrc RegWrite Instruction (25-21] PC Read address Read register 1 Read Instruction (20-16] Read data...
For the single-cycle ARM Thumb datapath discussed in class, what is the decimal value of the lower register file read address input (the one after the mux) while executing the instruction ANDS R3, R4? The table below contains the hexadecimal values of some registers before the instruction is executed. R2 18 R3 69 R4 99
For the single-cycle ARM Thumb datapath discussed in class, what is the decimal value of lower input to the ALU (the one after the mux) while executing the instruction LDR R4, [R2, #4]? The table below contains the decimal values of some registers before the instruction is executed. R2 309 R3 733 R4 1,054 PC 32,077
Given a single cycle datapath processor with a single stuck-at-1 fault at the ALUSrc control signal (i.e. regardless of what it should be, the signal is always one) which of the following instructions will FAIL? (mark ALL that will FAIL) a) lw b) sw c) add d) ori e) beq f) J