Implement an 8 bit register in VHDL/Verilog using Model Sim software. Show two test cases for...

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Implement an 8 bit register in VHDL/Verilog using Model Sim software. Show two test cases for...

Implement an 8 bit register in VHDL/Verilog using Model Sim software. Show two test cases for data read and write into the register.

The register has an enable and reset signal. When the reset is high the register should be cleared. When the enable is high and reset is low, data should be written into the register.

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Answer 1

Answer #1

ANSWER :

file dff.v

module dff(
input clk,reset,enable,d,
output reg Q
);
always@(posedge clk)
begin
if(reset)
Q <=0;
else if(enable)
Q <=d;
end

endmodule

file 8_bit_reg,v

module register(
input [7:0] in,
input clk,
output [7:0] out

);

dff u[7:0](clk,0,1,in,out);

endmodule

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Answer 2

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