Question

I have to be able to explain in layman term and teach a class on how to "design a synchronous counter in VHDL"

Answer 1

Synchronous Counter: Counts at every clock event. Start with zero with reset input.

Below is a VHDL code for a four-bit synchronous counter with a clock rising edge.

/*VHDL Code*/
library IEEE; -- importing library
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--- module declared for a four-bit synchronous counter

entity FourBitSyncCounter is

Port (
       clock_in,RST : in STD_LOGIC; -- input clock and reset signal
       count_value : inout STD_LOGIC_VECTOR (3 downto 0) -- output counter 4 bit
   );

end FourBitSyncCounter;

architecture Behavioral of FourBitSyncCounter is -- Behavioral mode architecture defined

begin

   process (clock_in,reset_in) -- Process with clock and reset as sensitivity list

   begin

       if (RST = '1') then

           count_value <= "0000"; -- Counter will be zero if reset signal is high

       elsif(rising_edge(clock_in))then -- At every rising edge of the clock counter will be incremented by one

           count_value <= count_value + 1; -- It will be overflow after 15₁₀ (1111₂) value

       end if;

   end process;

end Behavioral; -- End of the architecture defined