Question

1. Suppose an instruction takes four cycles to execute in a nonpipelined CPU: one cycle to fetch the instruction, one cycle to decode the instruction, one cycle to perform the ALU operation, and one cycle to store the result. In a CPU with a four-stage pipeline, that instruction still takes four cycles to execute, so how can we say the pipeline speeds up the execution of the program?

Answer 1

The same time is required because only one instruction in taken in consideration in both the cases, and the next step depends upon the previous step of the instruction. Let me explain with an example

Now, suppose we have two statements ADD 2,5 and ADD 3,4, following are the steps in a non-pipelined architecture:

• Fetch the instruction ADD 2,5 - 1 cycle required.
• Decode the statement. Now the thing is to decode a statement, we need to fetch it first. So this comes after the fetch statement. - 1 cycle required
• Perform the ALU operation. To perform a operation we need to perform the previous 2 statements first. - 1 cycle required.
• Store result. To store the value in result we first need to perform the previous three cycles first. - 1 cycle required.

Four cycles required for instruction ADD 2,5, similarly four more cycles are required for the instruction ADD 3,4.

Total cycles required = 8

Now for two instructions ADD 2,5 and ADD 3,4, following are the steps in a pipelined architecture:

• Fetch the instruction ADD 2,5 - 1 cycle required.
• Decode the instruction 1. Since it is pipelined architecture we can fetch the instruction ADD 3,4 here as well. - 1 cycle required
• Perform the ALU operation on instruction 1. And decode instruction 2. - 1 cycle required.
• Store result of the first instruction. And perform ALU operation on the second on. - 1 cycle required.
• Store result of the second instruction. - 1 cycle required

Total cycles required = 5.

Since it is a four stage pipeline architecture, you can pipeline four instructions at a time. 8 instructions cycles will be required for four instructions. Whereas if it was non-pipelined, 16 cycles would have been required.