Question

Explain about n bit Serial in Parallel Out Shift registers with a neat circuit diagram and discuss in detail about the data movements in SIPO Shift register.

Answer 1

Here a 4-bit SIPO shift register is shown below. In the case of n-bit SIPO shift register, there will be n number of registers connected in the configuration as shown in the figure below.

The input pulse to the serial input be 0-1-0 fed to FFA

Let us consider that initially, all the Flip flops are in RESET condition. Thus the output of all Flip flops is "0" i.e. no parallel data output.

1) A high input "1" is fed to the input of FFA. With the first clock pulse, the output of FFA i.e. Q_A will also be high (1), whereas the output of the rest of the FF will be low (0).

2) With the second clock pulse, the output of the FFA will change to low (0). And the output of FFB i.e. Q_B change to high (1) as its input D has high input (1) from Q_A .​​ Thus we can say that logic "1" has shifted one place along the register towards the right

3) When the third clock pulse is applied, then this logic "1" shifts to the output Q_C of FFC. Similarily with the next clock pulse, the output of previous FF shifts one place towards the right.  

Increasing clock pulse has the effect of moving the data contents of each stage one position to the right, and this is seen in the table below before the full data value of 0-0-0-1 is stored in the register.

This data value can now be read directly from the outputs of QA to QD.