Question

This is a whole question with no figure in logic design class.

1. A 100 MHz crystal has been purchased for use in an electronic design. The crystal has the following specifications:
   1. 30 ppm base tolerance
   2. 20 ppm / year aging tolerance

What is the specified period (T) with no tolerances applied?

What range of periods is possible with the part in its initial state?

After the part has been in operation for 5 years, what range of periods is possible for it?

2. For the part cited in Question #1, the rest of the design requires a period of at least 9.9997 nSecs in order to properly function.   Assuming that the part is initially at the slow (i.e. low frequency) spec limit, how many years will the system run reliably? Assume the worst case scenario of a part getting faster (i.e., higher frequency) as it ages.

3. A design has been built with a 10 MHz oscillator. The technology parameters for the design are:

• Rising Ouput:   Base = 4 nSecs, Load Adder = 1.0 nSecs/Load
• Falling Output: Base = 2 nSecs, Load Adder = 0.5 nSecs/Load

The average load on each block is 2 units and the design is built entirely from NANDs.

• How many blocks can the longest path contain?  
• What margin is left in the design for oscillator base tolerance or drift?

4. For the design cited in Problem #3, the longest path contains 16 blocks.   What is the largest value the blocks can tolerate for average loading and still have a 4 nSec margin in the cycle time?