Question

#8 Verilog

Program 6-6 Test bench for a 2-to-4 decoder tinescale i ne 7 100 ps nodule Vr2to4dec tb O integer i, errors; reg (3:0] expectY; Vratoidec, UUT AO(AOs), A1 CA1s), .ENCENa), I/ Instantiate unit under initial begin errors 0: for (i-o; ic-7: 1-1+1) begin // Apply test input combination // Expect no outputs asserted it E #10 ; expecty 4'b0000 if' (ENs-1 ) expectrais,AOs)) 1 'b1; // Else output {A1,AO} should bL if (fr3s, Y2s, Y1s, YOs expectY) begin EN A1AO %b %b%b, Y3Y2YIYO- %b%b%b%b" $display ( "Error: errors-errors+ 1; end end $display("Test complete, %d errors" , errors); end endnodule G- wx,y(L,2,3,5) n the test bench of Program 6-6 for the 2-to-4 decoder module Vr2to4decs 6-1, showing that there are no errors. Then do three more runs, each ing or deleting just one character in Vr2to4dec s. resulting in the test. bench reporting 2, 4, and 8 errors. the author ran the test bench of Program 6-6 for his initial version of the 6Wasi decoder module Vr2to4dec.d in Program 6-2, it detected a big error in a When the author ran th

Answer 1

tnput a,5, en; End mDdlue