Prof. Tassos Dimitriou Homework 3 Deadline: Monday, April 1, 2019, IN CLASS Problem 3 [10 points ...
part c
Problem 3 [10 points a) (5 points) Construct a circuit that takes as input a 3-bit number X-XXXo and increments it by one. L.e. if the input is 101 the output should be 110. Use only half adders. b) Construct a circuit that takes as input a 3-bit number X-XXxo and decrements it by one 1. (5 points) Show the truth table of the circuit. Then use a decoder and additional gates to implement it. So Ys Y2...
1. Using only half adders, design a four-bit incrementer circuit (a circuit that adds 1 to a four- bit binary number). 2. Using only 2-to-4 line decoders with enable, construct a 4-to-16 line decoder. 3. Using a decoder and external gates, design the combinational circuit defined by the following three Boolean functions: F = x'y'z' + x2 F2 = xy'z' + x'y F3 = x'y'z + xy
Student ID K-map to simply the function f e and "d" is the least si (3 points each) CO: 3] 3. Five bits of information and a parity bit are to be transmitted on a noisy channel. The transmittor a. the parity checker circuits using Only 3-imput logic gates where the unused inpunts)-if any- must be connected to either O or 1, as appropriate. (show the cireuit). (3 points for each circuit for a total of 6 points) ver have...
A comparator circuit has two 1-bit inputs A and B and three 1-bit outputs G (greater), E (equal), and L (less than). That is, G is 1 if A > B (0 otherwise), E is 1 if A == B (0 otherwise), and L is 1 if A < B (0 otherwise). a. Draw the truth table for a 1-bit comparator (the table has 2 inputs and 3 outputs). b. Implement G, E, and L circuits using only...
Design a combinational circuit that adds 1 to 3-bit unsigned binary number and produces an unsigned binary result. Do the following: (1) determine the number of inputs/outputs, (2) write the truth table, (3) simplify the output functions by using maps and (4) draw the logic diagram by using AND OR and NOT gates. Show the truth table, the map, and the logic diagram. Do NOT use adders.
Please do problem 2 and 3
Complete the following homework problems. Show all work (making answers for clarity sure it is legible) and circle all Problem 1 w3 X A w4 w1 C D Y w2 Determine Boolean functions for intermediate outputs wl,w2,w3, and w4 as well as the output signals X and Y. b) a) Construct a truth table showing the intermediate outputs wl,w2,w3, and w4 as well as the output signals X and Y Use K-maps to find...
1. (15 pts) Simplify the following Boolean functions using K-maps: a. F(x,y,z) = (1,4,5,6,7) b. F(x, y, z) = (xy + xyz + xyz c. F(A,B,C,D) = 20,2,4,5,6,7,8,10,13,15) d. F(A,B,C,D) = A'B'C'D' + AB'C + B'CD' + ABCD' + BC'D e. F(A,B,C,D,E) = (0,1,4,5,16,17,21,25,29) 2. (12 pts) Consider the combinational logic circuit below and answer the following: a. Derive the Boolean expressions for Fi and F2 as functions of A, B, C, and D. b. List the complete truth table...
Please solve
the problems from 1_5
Digital
system
Complete the following homework problems. Show all work (making sure it is legible) and circle all answers for clarity Problem 1 w3 w4 B w1 a) Determine Boolean functions for intermediate outputs w,w2,w3, and w4 as well as the output signals X and Y. b) Construct a truth table showing the intermediate outputs wl,w2,w3, and w4 as well as the output signals X and Y c) Use K-maps to find simplified expressions...
Building and testing basic combinational circuits using Verilog HDL Description: Build and test the following circuits using gate-level modeling in Verilog HDL. 1. 3-input majority function. 2. Conditional inverter (see the table below: x - control input, y - data input). Do NOT use XOR gates for the implementation. x y Output 0 y 1 y' 3. Two-input multiplexer (see the table below: x,y - data inputs, z - control input). z Output 0 x 1 y 4. 1-bit half...
partb
Problem 2 [15 points] Consider again the function F(x, y, z, w) from problem 1. (a) [5 points) Implement F using one 2-1 MUX and additional gates (show work for all choices for the selection variables) (b) [5 points] Implement F using only 2-to-1 MUXes and no additional gates (this means that NOT gates are not available as well). Explain how dy ny rx 0