Question

3. 15 points Timers: Suppose that our timers on the MSP430 are set with NC 01, ID-8, and IDEX-3. Assume the CPU clock is 25MHz. (a) What is the CPU clock's time per cycle? (b) What is the timer frequency? (c) What is the cycle time of the timer? (d) What value of TACCRO will set the time delay between TAIFGs to ap- proximately lms?

Answer 1

Answer :- a) The CPU frequency = 25 MHz. Thus CPU clock time per cycle = 1/25 us = 0.04 us = 40 ns.

Answer :- b) The input divider value is 8 means clock gets divided by 8 and it becomes 25/8 MHz. Then IDEX is 3, so final clock for timer has frequency = 25/(8*3) MHz =  1.0416 MHz.

Answer :- c) The cycle time = 24/25 us = 960 ns.

Answer :- d) Let n be the count value then,

n*(24/25)*10^-6 = 1*10^-3

=> n = 1041.66

Hence TACCR0 must be loaded with value 1042.